M62342GP

Rev.1.0, Sep.19.2003, page 2 of 6

Block Diagram

8

+-

+-

V

8-bit uppe

segment R-2R

8-bit uppe

segment R-2R

CC

LD

CLK

DI

GND

N.C.

58

7

6

5

23

1

Power-on

reset

10-bit shift register

Channel

decoder

8-bit latch

8-bit latch

Pin Description

Pin No.

Symbol

Function

6

DI

Serial data input pin. Inputs serial data with a 10-bit data length.

7

CLK

Serial clock input pin. Input signal from DI pin is input to 10-bit shift register at rise of

shift clock.

8

LD

Load pin. When “H” level is input to LD pin, value in 10-bit shift register is loaded into

decoder and D-A output register.

1

Ao1

2

Ao2

8-bit resolution D-A converter output pins

(After power-on, all channels are reset and DAC data 00h is output.)

3

N.C.

(Not connected)

4

Vcc

Power supply voltage pin

5

GND

GND pin