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PHT1N52S Datasheet(PDF) 2 Page - NXP Semiconductors |
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PHT1N52S Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 5 page ![]() Philips Semiconductors Objective specification PowerMOS transistor PHT1N52S THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT R th j-sp Thermal resistance junction to - - 15 K/W solder point R th j-a Thermal resistance junction to pcb mounted; minimum footprint - 156 - K/W ambient pcb mounted; pad area as in fig:2 - 70 - K/W STATIC CHARACTERISTICS T mb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V (BR)DSS Drain-source breakdown volt- V GS = 0 V; ID = 0.25 mA 520 - - V age V GS(TO) Gate threshold voltage V DS = VGS; ID = 0.25 mA 2.0 3.0 4.0 V I DSS Drain-source leakage current V DS = 500 V; VGS = 0 V; Tj = 25 ˚C - 1 100 µA V DS = 400 V; VGS = 0 V; Tj = 125 ˚C - 0.1 1.0 mA I GSS Gate-source leakage current V GS = ±35 V; VDS = 0 V - 4 100 nA R DS(ON) Drain-source on-state resis- V GS = 10 V; ID = 1 A - 7.9 10 Ω tance V SD Source-drain diode forward I F = 2 A ;VGS = 0 V - 0.85 1.2 V voltage DYNAMIC CHARACTERISTICS T mb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT g fs Forward transconductance V DS = 15 V; ID = 1 A 0.5 0.8 - S C iss Input capacitance V GS = 0 V; VDS = 25 V; f = 1 MHz - 75 100 pF C oss Output capacitance - 10 15 pF C rss Feedback capacitance - 5 10 pF Q g(tot) Total gate charge V GS = 10 V; ID = 2 A; VDS = 400 V - 5 - nC Q gs Gate to source charge - .5 - nC Q gd Gate to drain (Miller) charge - 3 - nC t d on Turn-on delay time V DD = 30 V; ID = 2 A; - 5 10 ns t r Turn-on rise time V GS = 10 V; RGS = 50 Ω; - 15 20 ns t d off Turn-off delay time R GEN = 50 Ω - 1520ns t f Turn-off fall time - 7 15 ns t rr Source-drain diode Reverse I F = 2 A; -dIF/dt = 100 A/µs; - 150 - ns recovery time Q rr Source-drain diode Reverse V GS = 0 V; VR = 100 V - 1.5 - µC recovery charge February 1998 2 Rev 1.000 |
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