Philips Semiconductors

Objective specification

PowerMOS transistor

PHT1N60R

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel

enhancement

mode

SYMBOL

PARAMETER

MAX.

UNIT

field-effect power transistor in a

plastic envelope suitable for surface

V

DS

Drain-source voltage

600

V

mounting featuring high avalanche

I

D

Drain current (DC)

0.53

A

energy capability, stable blocking

P

tot

Total power dissipation

1.8

W

voltage, fast switching and high

R

DS(ON)

Drain-source on-state resistance

16.0

Ω

thermal

cycling

performance.

Intended for use in Compact Fluor-

escent Lights (CFL) and general

purpose switching applications.

PINNING - SOT223

PIN CONFIGURATION

SYMBOL

PIN

DESCRIPTION

1

gate

2

drain

3

source

4

drain (tab)

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DS

Drain-source voltage

-

600

V

V

DGR

Drain-gate voltage

R

-

600

V

±V

GS

Gate-source voltage

-

30

V

I

D

Drain current (DC)

T

25 ˚C

-

0.53

A

T

-

0.4

A

I

DM

Drain current (pulse peak

T

25 ˚C

-

2.12

A

value)

I

DR

Source-drain diode current

T

25 ˚C

-

0.53

A

(DC)

I

DRM

Source-drain diode current

T

25 ˚C

-

2.12

A

(pulse peak value)

P

tot

Total power dissipation

T

25 ˚C

-

1.8

W

T

stg

Storage temperature

-55

150

˚C

T

j

Junction temperature

-

150

˚C

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

W

DSS

Drain-source non-repetitive

I

unclamped inductive turn-off

R

energy

T

-

20

mJ

T

-

8

mJ

W

DSR

1

Drain-source repetitive

I

-

3.6

mJ

unclamped inductive turn-off

R

energy

1. Pulse width and frequency limited by T

j(max)

4

1

23

d

g

s

February 1998

1

Rev 1.000