PHT6N03LT datasheet(5/6 Pages) PHILIPS

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Philips Semiconductors

Product specification

TrenchMOS

™ transistor

PHT6N03LT

Logic level FET

Fig.11. Sub-threshold drain current.

D = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS

Fig.12. Typical capacitances, C

iss, Coss, Crss.

C = f(V

DS); conditions: VGS = 0 V; f = 1 MHz

Fig.13. Typical turn-on gate-charge characteristics.

GS = f(QG); conditions: ID = 5.9 A; parameter VDS

Fig.14. Typical reverse diode current.

F = f(VSDS); conditions: VGS = 0 V; parameter Tj

Fig.15. Normalised avalanche energy rating.

DSS% = f(Tamb); conditions: ID = 5.9 A

Fig.16. Avalanche energy test circuit.

0.5

1.5

2.5

1E-05

1E-04

1E-03

1E-02

1E-01

Sub-Threshold Conduction

typ

98%

0.5

1.5

9830-30

VSDS / V

IF / A

Tj / C = 150

0.1

100

1000

10000

9528-30

VDS / V

C / pF

Ciss

Coss

Crss

100

120

140

120

110

100

WDSS%

Ambient temperature, Tamb (C)

9830-30

QG / nC

VGS / V

VDS / V = 6

T.U.T.

VDD

RGS

R 01

VDS

-ID/100

shunt

VGS

DSS = 0.5 ⋅ LID

⋅ BV

DSS/(BVDSS − VDD)

January 1998

Rev 1.300

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