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OV9120 Datasheet(PDF) 13 Page - OmniVision Technologies, Inc. |
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OV9120 Datasheet(HTML) 13 Page - OmniVision Technologies, Inc. |
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13 / 24 page ![]() DATASHEET OV9620/OV9120 Datasheet Doc #DS102 © OmniVision Technologies Inc., 2002, version 2.0 Page 12 Video Output The video output port of the OV9620/OV9120 CameraChip provides various output formats/standard options to suit many different application requirements. Table 6, Digital Output Format indicates the output formats available. These formats are user-programmable through the SCCB interface. Table 6. Digital Output Format Progressive Format Pixel Clock 1280x1024 SXGA 640x480 VGA RGB Raw Data 10-bit Y Y B/W Y Y Digital Video Port Y Y ZV Port Interface Y Y (“Y” indicates mode/combination is supported by OV9620/OV9120) RGB Raw Data Output The OV9620/OV9120 CameraChip offers 10-bit RGB Raw Data output. B/W Output The CameraChip can be configured for use as a black and white imaging device. The vertical resolution is higher than in color mode. Digital Video Port MSB/LSB Swap OV9620/OV9120 has a 10-bit digital video port. The MSB and LSB can be swapped with the control registers. Figure 16 shows some examples of connections with external devices. Figure 17. Example of Connection d3 MSB d9 d8 d7 d6 d5 d4 d2 d1 LSB d0 d3 d9 d8 d7 d6 d5 d4 d2 d1 d0 Default 10bit Connection d3 LSB d9 d8 d7 d6 d5 d4 d2 d1 MSB d0 d6 d0 d1 d2 d3 d4 d5 d7 d8 d9 Swap 10bit Connection d3 MSB d9 d8 d7 d6 d5 d4 d2 d1 LSB d0 d3 d7 d6 d5 d4 d2 d1 d0 Default 8bit Connection d3 LSB d9 d8 d7 d6 d5 d4 d2 d1 MSB d0 d6 d0 d1 d2 d3 d4 d5 d7 Swap 8bit Connection Line/Pixel Timing The OV9620/OV9120 digital video port can be programmed to work in either master or slave mode. In both master and slave modes, pixel data output is synchronous with PCLK (or MCLK if port is a slave), HREF and VSYNC. The default PCLK edge for valid data is the negative edge but may be programmed with register [15] bit4 for the positive edge. Basic line/pixel output timing is illustrated in Figures 17 and 18. To minimize image capture circuitry and conserve memory space, PCLK output can be programmed with register [15] bit5 to be gated by the active video period as defined by the HREF signal. See Figure 16 for illustration. Figure 18. PCLK Output Only at Valid Pixels HREF VSYNC PCLK PCLK active edge negative PCLK PCLK active edge positive |
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