6.4 Device Functional Modes

The DACx3508 has two modes of operation: normal and power-down.

6.4.1 Power-Down Mode

The DACx3508 DAC output amplifiers can be independently or globally powered down (10 kΩ to AGND) through

the DEVICE_CONFIG register. In global power down mode, the device consumes 50 µA (VDD = 1.8 V). At

power-up, all output channels buffer amplifiers start in power-down (10 kΩ-AGND) mode until a power-up

command is issued by writing 0 to the per-channel power-down register bits.

6.5 Programming

6.5.1 Serial Peripheral Interface (SPI)

The DACx3508 supports a three-wire SPI with write-only functionality. An SPI write cycle for DACx3508 is

initiated by asserting the SYNC pin low. The serial clock, SCLK, can be a continuous or gated clock. SDI data

are clocked on SCLK falling edges. The SPI frame for DACx3508 is 24 bits long; therefore, the SYNC pin must

stay low for at least 24 SCLK falling edges. The write cycle ends when the SYNC pin is deasserted high. If the

write cycle contains less than the minimum clock edges, the communication is ignored. If the write cycle contains

more than the minimum clock edges, only the first 24 bits are used by the device.

Table 6-1 describes the format for the 24-bit SPI write access cycle. The first byte input to SDI is the instruction

cycle. The instruction cycle identifies the request as the 8-bit address to be written. The last 16 bits in the cycle

form the data cycle.

Table 6-1. SPI Write Access Cycle

BIT

FIELD

DESCRIPTION

23-16

A[7:0]

Register address: specifies the register to be accessed during the write operation.

15-0

DI[15:0]

Data cycle bits: The data cycle bits are the values written to the register with

address A[7:0].

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DAC43508, DAC53508, DAC63508

SLASF08A – DECEMBER 2021 – REVISED MAY 2024

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