MC68HC08AB16AD datasheet(73/380 Pages) FREESCALE

73 / 380 page

MC68HC08AB16A — Rev. 2.1

Technical Data

Freescale Semiconductor

These two read/write registers are respectively loaded with the contents

of the EEPROM timebase divider mask option registers (EEDIVHMOR

and EEDIVLMOR) after a reset.

EEDIVSECD — EEPROM Divider Security Disable

This bit enables/disables the security feature of the EEDIV registers.

When EEDIV security feature is enabled, the state of the registers

EEDIVH and EEDIVL are locked (including this EEDIVSECD bit).

1 = EEDIV security feature disabled

0 = EEDIV security feature enabled

EEDIV[10:0] — EEPROM Timebase Prescaler

These prescaler bits store the value of EEDIV which is used as the

divisor to derive a timebase of 35

µs from the selected reference clock

source (CGMXCLK or bus clock, see 6.5 Mask Option Register B)

for the EEPROM related internal timer and circuits. EEDIV[10:0] bits

are readable at any time. They are writable when EELAT=0 and

EEDIVSECD=1.

The EEDIV value is calculated by the following formula:

EEDIV = INT

[Reference frequency (Hz) × 35 × 10–6 + 0.5]

Address:

$FE1A

Bit 7

654321

Bit 0

Read:

EEDIVSECD

RRRR

EEDIV10

EEDIV9

EEDIV8

Write:

Reset:

Contents of EEDIVHMOR ($FE10)

Figure 5-5. EEPROM Divider Register High (EEDIVH)

Address:

$FE1B

Bit 7

654321

Bit 0

Read:

EEDIV7

EEDIV6

EEDIV5

EEDIV4

EEDIV3

EEDIV2

EEDIV1

EEDIV0

Write:

Reset:

Contents of EEDIVLMOR ($FE11)

Figure 5-6. EEPROM Divider Register Low (EEDIVL)

MC68HC08AB16AD Datasheet(PDF) 73 Page - Freescale Semiconductor, Inc

MC68HC08AB16AD Datasheet(HTML) 73 Page - Freescale Semiconductor, Inc

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