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TUSB564 Datasheet(PDF) 10 Page - Texas Instruments |
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TUSB564 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 54 page ![]() 5.5 Electrical Characteristics (continued) over operating free-air temperature and voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RON- MISMATCH ΔON resistance mismatch within pair VCC = 3.3V; VIN = 0V to 0.4V for AUXP; VIN= 2.7V to 3.6V for AUXN 1 Ω RON_FLAT ON resistance flatness (RONmax–RON min) measured at identical VCC and temperature VCC = 3.3V; VIN = 0V to 0.4V for AUXP; VIN = 2.7V to 3.6V for AUXN 2 Ω VAUXP_DC _CM AUX channel DC common-mode voltage for AUXP and SBU2. VCC = 3.3V 0 0.4 V VAUXN_D C_CM AUX channel DC common-mode voltage for AUXN and SBU1 VCC = 3.3V 2.7 3.6 V CAUX_ON ON-state capacitance VCC = 3.3V; CTL1 = 1; VIN = 0V or 3.3V 4 7 pF CAUX_OFF OFF-state capacitance VCC = 3.3V; CTL1 = 0; VIN = 0V or 3.3V 3 6 pF 5.6 Timing Requirements MIN NOM MAX UNIT USB3 tIDLEEntry, Delay from U0 to electrical idle 10 ns tIDLEExit_U1 U1 exit time: break in electrical idle to the transmission of LFPS 6 ns tIDLEExit_U2U 3 U2/U3 exit time: break in electrical idle to transmission of LFPS 10 µs tRXDET_INTV L RX detect interval while in disconnect 12 ms tIDLEExit_DIS C Disconnect exit time 10 µs tExit_SHTDN Shutdown exit time (CTL0 = VCC/2 to U2/U3) 1 ms tDIFF_DLY Differential propagation delay (20% to 80% of differential voltage measured 1.7 inch from the output pin) 300 ps tPWRUPACTI VE Time when Vcc reaches 70% to device active 1 ms tR, tF Output rise/fall time 40 ps tRF-MM Output rise/fall time mismatch (20% to 80% of differential voltage measured 1.7 inch from the output pin) 5 ps 5.7 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUXp/n and SBU1/2 TAUX_PD Switch propagation delay 1400 ps TAUX_SW_ OFF Switching time CTL1 to switch OFF. Not including TCTL1_DEBOUNCE. 7500 ns TAUX_SW_ ON Switching time CTL1 to switch ON 3000 ns TAUX_INT RA Intra-pair output skew 400 ps USB3.1 and DisplayPort mode transition requirement (GPIO mode) TGP_USB_ 4DP Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode to 4-Lane DisplayPort mode or vice versa 4 µs TUSB564-Q1 SLLSFO9 – MAY 2024 www.ti.com 10 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TUSB564-Q1 |
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