XR19L210

21

REV. 1.0.1

SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER

4.4.2

IER versus Receive/Transmit FIFO Polled Mode Operation

When FCR bit-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR19L210 in the FIFO

polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can

be used in the polled mode by selecting respective transmit or receive control bit(s).

A. LSR BIT-0 indicates there is data in RHR or RX FIFO.

B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.

C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.

D. LSR BIT-5 indicates THR is empty.

E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.

F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.

IER[0]: RHR Interrupt Enable

The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when

the receive FIFO has reached the programmed trigger level in the FIFO mode.

IER[1]: THR Interrupt Enable

This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-

FIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is

empty when this bit is enabled, an interrupt will be generated.

IER[2]: Receive Line Status Interrupt Enable

If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller

about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the

character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of

the FIFO.

IER[3]: Modem Status Interrupt Enable

IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)

IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)

details.

IER[6]: RTS Output Interrupt Enable (requires EFR bit-4=1)

low to high.