Philips Semiconductors RF Communications Products

Product specification

SA701

Divide by: 128/129-64/65 dual modulus low power

ECL prescaler

June 17, 1993

4

DC ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

MIN

TYP

MAX

Power supply voltage range

2.7

6.0

V

Supply current

No load

4.5

mA

Output high level

V

Output low level

V

MC input high threshold

2.0

V

MC input low threshold

–0.3

0.8

V

SW input high threshold

2.0

V

SW input low threshold

–0.3

0.8

V

MC input high current

0.1

50

µA

MC input low current

–100

–30

µA

SW input high current

35

100

µA

SW input low current

–50

–0.1

µA

AC ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

MIN

TYP

MAX

1000pF input coupling

0.05

2.0

Input signal frequency

0

1.1

GHz

1000pF input coupling

1.1

GHz

Differential input resistance

DC measurement

5

k

Ω

Output voltage

1.6

1.2

5

ns

0

ns

Propagation time

10

ns

NOTES:

1. Maximum limit is not tested, however, it is guaranteed by design and characterization.

DESCRIPTION OF OPERATION

The SA701 comprises a frequency divider

circuit implemented using a divide by 4 or 5

synchronous prescaler followed by a 5 stage

synchronous counter, see BLOCK

DIAGRAM. The normal operating mode is for

SW (Modulus Set Switch) input to be set low

and MC (Modulus Control) input to be set

high in which case the circuit comprises a

divide by 128. For divide by 129 the MC

signal is forced low, causing the prescaler

circuit to switch into divide by 5 operation for

the last cycle of the synchronous counter.

Similarly, for divide by 64 and 65 the SA701

will generate those respective moduli with the

SW signal forced high, in which the fourth

stage of the synchronous divider is

bypassed. A truth table for the modulus

values is given below:

Table 1.

Modulus

MC

SW

128

1

0

129

0

0

64

1

1

65

0

1

For minimization of propagation delay effects,

the second divider circuit is synchronous to

the divide by 4/5 stage output.

The prescaler input is positive edge sensitive,

and the output at the final count is a falling

the input. The rising edge of the output

occurs at the count 64 for modulus 128/129

The SW input is not designed for

synchronous switching.

The MC and SW inputs are TTL compatible

threshold inputs operating at a reduced input

current. CMOS and low voltage interface

capability are allowed. The SW input has an

internal pull-down simplifying modulus group

selection. With SW open the divide by

128/129 mode is selected and with SW

The prescaler input is differential and ECL

compatible. The output is single-ended ECL

compatible.