SA702 datasheet(3/7 Pages) PHILIPS

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Philips Semiconductors RF Communications Products

Product specification

SA702

Divide by: 64/65/72 triple modulus low power

ECL prescaler

June 17, 1993

DC ELECTRICAL CHARACTERISTICS

The following DC specifications are valid for TA = 25°C and VCC = 3.0V; unless otherwise stated. Test circuit Figure 1.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

MIN

TYP

MAX

VCC

Power supply voltage range

fIN = 1GHz, input level = 0dBm

2.7

6.0

ICC

Supply current

No load

4.5

VOH

Output high level

IOUT = 1.2mA

VCC-1.4

VOL

Output low level

VCC-2.6

VIH

MC1 input high threshold

2.0

VCC

VIL

MC1 input low threshold

–0.3

0.8

VIH

MC2 input high threshold

2.0

VCC

VIL

MC2 input low threshold

–0.3

0.8

IIH

MC1 input high current

VMC1 = VCC = 6V

0.1

µA

IIL

MC1 input low current

VMC1 = 0V, VCC = 6V

–100

–30

µA

IIH

MC2 input high current

VMC2 = VCC = 6V

0.1

µA

IIL

MC2 input low current

VMC2 = 0V, VCC = 6V

–100

–30

µA

AC ELECTRICAL CHARACTERISTICS

These AC specifications are valid for fIN = 1GHz, input level = 0dBm, VCC = 3.0V and TA = 25°C; unless otherwise stated. Test circuit Fig. 1.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

MIN

TYP

MAX

VIN

Input signal amplitude1

1000pF input coupling

0.05

2.0

VP-P

fIN

Input signal frequency

Direct coupled input2

1.1

GHz

1000pF input coupling

1.1

GHz

RID

Differential input resistance

DC measurement

Ω

Output voltage

VCC = 5.0V

1.6

VP-P

VCC = 3.0V

1.2

VP-P

Modulus set-up time1

Modulus hold time1

tPD

Propagation time

NOTES:

1. Maximum limit is not tested, however, it is guaranteed by design and characterization.

2. For fIN < 50MHz, minimum input slew rate of 32V/µs is required.

DESCRIPTION OF OPERATION

The SA702 comprises a frequency divider

circuit implemented using a divide by 4 or 5

synchronous prescaler followed by a 5 stage

synchronous counter, see BLOCK

DIAGRAM. The normal operating mode is for

MC1 (Modulus Control) to be set high and

MC2 input to be set low in which case the

circuit comprises a divide by 64. For divide

by 65 the MC1 singal is forced low, causing

the prescaler circuit to switch into divide by 5

operation for the last cycle of the

synchronous counter. For divide by 72, MC2

is set high configuring the prescaler to divide

by 4 and the counter to divide by 18. A truth

table for the modulus values is given below:

Table 1.

Modulus

MC1

MC2

For minimization of propagation delay effects,

the second divider circuit is synchronous to

the divide by 4/5 stage output.

The prescaler input is positive edge sensitive,

and the output at the final count is a falling

edge with propagation delay tPD relative to

the input. The rising edge of the output

occurs at the count 32 with delay tPD.

The MC1 and MC2 inputs are TTL

compatible threshold inputs operating at a

reduced input current. CMOS and low

voltage interface capability are allowed.

The prescaler input is differential and ECL

compatible. The output is differential ECL

compatible.

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