1

2

3 4

8

7

6

5

V

C

FB

SS

Test

AGND

V

CC

PGND

V

SW

GM3255

AYWW

A = Assembly Location

Y = Year

W W = Work Week

Ordering Number

Package

Shipping

GM3255S8T

GM3255NS8T

GM3255S8R

GM3255NS8R

SOP - 8

NSOP - 8

SOP - 8

NSOP - 8

100 Units / Tube

100 Units / Tube

2,500 Units / Tape & Reel

2,500 Units / Tape & Reel

PIN DESCRIPTION

PIN NUMBER

PIN SYMBOL

FUNCTION

1

2

3

4

5

6

7

8

FB

Test

SS

AGND

PGND

Loop compensation pin. The V pin is the output of the error amplifier and is used for

C

loop compensation, current limit and start. Loop compensation can be implemented

by a simple RC network as shown in the application diagram on page 2 as R1 and C1.

Positive regulator feedback pin. This pin senses a positive output voltage and is

referenced to 1.276V. When the voltage at this pin falls below 0.4 V, chip switching

frequency reduces to 20% of the nominal frequency.

These pins are connected to internal test logic and should either be left floating or tied to

ground. Connection to a voltage between 9.5V and 15V shuts down the internal oscillator

and leaves the power switch running.

Synchronization and shutdown pin. This pin may be used to synchronize the part to

nearly twice the base frequency. ATTL low shut the part down and put it into low current

mode. If synchronization is not used, this pin should be either tied high or left floating for

normal operation.

Input power supply pin. This pin supplies power to the part and should have a bypass

capacitor connected to AGND.

Analog ground. This pin provides a clean ground for the controller circuitry ans should

not be in the path of large currents. The output voltage sensing resistors should be

connected to the IC substrate.

Power ground. This pin is the ground connection for the emitter of the power switching

transistor. Connection to a good ground plane is essential.

High current switch pin. This pin connects internally to the collector of the power switch.

The open voltage across the power switch can be as high as 40V. To minimize radiation,

use a trace as short as practical.

ABSOLUTE MAXIMUM RATINGS

PARAMETER

VALUE

UNITS

Package Thermal Resistance

Junction-to-Case, R

qJC

junction-to-Ambient, R

qJC

Junction Temperature Range, T

J

Storage Temperature Range, T

STG

ESD, Human Body Model

45

165

-40 to +150

-65 to +150

230

1.2

°C / W

°C / W

kV

°C

°C

°C

Lead Temperature (Peak)

(reflow - soldering 60

maximum above

183°C)

s ec.

2

* For detail Ordering Number identification, please see last page.

*

The maximum package power dissipation must be observed.