xr

XRT91L32

REV. 1.0.2

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

19

2.10

Receive Parallel Data Output Timing

The receive parallel data output from the STS-12/STM-4 or STS-3/STM-1 receiver will adhere to the setup and

hold times shown in Figure 10 ,Table 7, and Table 8. Table 9 shows the PECL and TTL output timing

specifications.

Receive high-speed serial clock period

1.608

ns

Receive parallel data output byte clock period

12.86

ns

Time the data is valid on RXDO[7:0] and FRAMEPULSE

before and after the rising edge of RXPCLKO

4

ns

Pulse width of frame detection pulse on FRAMEPULSE

12.86

ns

Receive high-speed serial clock period

6.43

ns

Receive parallel data output byte clock period

51.44

ns

Time the data is valid on RXDO[7:0] and FRAMEPULSE

before and after the rising edge of RXPCLKO

22

ns

Pulse width of frame detection pulse on FRAMEPULSE

51.44

ns

RXPCLKO

RXDO[7:0]

RXIP

RXIN

FRAMEPULSE

A1

A2

A2

A2

A2