SAB9082 datasheet(2/24 Pages) PHILIPS

2 / 24 page

1999 Nov 12

Philips Semiconductors

Preliminary speciﬁcation

NTSC Picture-In-Picture (PIP) controller

SAB9082

FEATURES

• Double window Picture-in-Picture (PIP) in interlaced or

non-interlaced mode at 8-bit resolution

• Internal 1-Mbit DRAM

• Three 8-bit Analog-to-Digital Converters (ADCs) (7-bit

performance) with clamp circuit for each acquisition

channel

• One PLL which generates the line-locked clocks for the

subchannel

• One PLL which generates the line-locked clocks for the

main and display channels

• Three 8-bit Digital-to-Analog Converters (DACs)

• Linear zoom in both horizontal and vertical directions for

the subchannel

• Linear zoom in horizontal direction for the main channel

• Three multistandard PIP modes are available.

GENERAL DESCRIPTION

The SAB9082 is an NTSC PIP controller which can be

used in double window applications. The SAB9082 inserts

one or two live video signals with reduced size into another

live video signal. The incoming video signals are expected

to be analog baseband signals.

The conversion to the digital environment is done on chip

with ADCs. Processing and storage of the video data is

done entirely in the digital domain. The conversion back to

the analog domain is done by means of DACs.

Internal clocks are generated by PLLs which lock on to the

applied horizontal and vertical syncs.

The main input channel is compressed horizontally by a

factor of two and directly fed to the output. After

compression, a horizontal expansion of two is possible for

the main channel.

The subchannel is also compressed horizontally by a

factor of two but stored in memory before it is fed to the

outputs.

The SAB9082 can also create three multistandard PIP

modes, one with three PIPs placed in a column (MP3) and

two with two columns of three PIPs (MP6, MP6S).

The reduction factors of these PIPs are horizontal 1

⁄4 and

vertical 1

⁄3. In the first two modes, the column(s) can be

placed on the left or right side of the screen.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

VDDD

digital supply voltage

3.0

3.3

3.6

VDDA

analog supply voltage

3.0

3.3

3.6

IDDD

digital supply current

−

IDDA

analog supply current

140

165

210

PLL

fclk(sys)

system clock frequency

1792

× fHSYNC

−

MHz

Bloop

loop bandwidth

−

kHz

tjitter

short-term stability

peak-to-peak jitter for 64

µs −−

4ns

damping factor

−

0.7

−

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

SAB9082H

QFP100

plastic quad ﬂat package; 100 leads (lead length 1.95 mm);

body 14

× 20 × 2.8 mm

SOT317-2

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