SST26VF032B-104ISLASHSM datasheet(26/82 Pages) MICROCHIP

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SST26VF032B/SST26VF032BA

DS20005218K-page 26

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5.18

Block Erase

The Block Erase instruction clears all bits in the

selected block to ‘1’. Block sizes can be 8-Kbyte,

32-Kbyte or 64-Kbyte depending on address, see

Figure 3-1, Memory Map, for details. A Block Erase

instruction applied to a protected memory area will be

ignored. Prior to any write operation, execute the WREN

instruction. Keep CE# active-low for the duration of any

command sequence.

To execute a Block Erase operation, the host drives

CE# low then sends the Block Erase command cycle

(D8H), three address cycles, then drives CE# high.

Address bits AMS-A13 determine the block address

(BAX); the remaining address bits can be VIL or VIH. For

32-Kbyte blocks, A14:A13 can be VIL or VIH; for

64-Kbyte blocks, A15:A13 can be VIL or VIH. Poll the

BUSY bit in the STATUS register, or wait TBE, for the

completion of the internal, self-timed, Block Erase

operation. See Figure 5-21 and Figure 5-22 for the

Block Erase sequence.

FIGURE 5-21:

BLOCK-ERASE SEQUENCE (SQI)

FIGURE 5-22:

BLOCK-ERASE SEQUENCE (SPI)

Note:

MSN = Most Significant Nibble, LSN = Least Significant Nibble C[1:0] = D8H

MODE 3

SCK

SIO[3:0]

CE#

C1 C0

MODE 0

A5 A4

MSN LSN

A3 A2

A1 A0

CE#

SCK

ADDR

01 2 3 4 5 6 7 8

ADDR

High-Impedance

15 16

23 24

MODE 0

MODE 3

MSB

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