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S71PL129JC0 Datasheet(PDF) 110 Page - SPANSION |
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S71PL129JC0 Datasheet(HTML) 110 Page - SPANSION |
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110 / 153 page  108 S71PL129JC0/S71PL129JB0/S71PL129JA0 S71PL129Jxx_00_A8 October 28, 2005 Advance Info rmation Timing Diagrams Read Cycle twc Write cycle time 70 20k ns tcw Chipselect to end of write 60 ns tas Address set up Time 0ns taw Address valid to end of write 60 ns tbw UB#, LB# valid to end of write 60 ns twp Write pulse width 50 20k ns twr Write recovery time 0ns twhz Write to output High-Z 5ns tdw Data to write time overlap 20 ns tdh Data hold from write time 0ns tow End write to output Low-Z 5 tow Write high pulse width 7.5 ns tpc Page read cycle 20 20k ns tpa Page address access time 20 ns twpc Page write cycle 20 20k ns tcp Chip select high pulse width 10 ns Figure 33. Timing of Read Cycle (CE# = OE# = VIL, WE# = ZZ# = VIH) Page Mode Performance Grade -70 Density 64Mb pSRAM 3 Volt Symbol Parameter Min Max Units Address Data Out tRC tAA tOH Data Valid Previous Data Valid |
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