SST29SF040 datasheet(3/25 Pages) SST

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Data Sheet

2 Mbit / 4 Mbit Small-Sector Flash

SST29SF020 / SST29SF040

SST29VF020 / SST29VF040

S71160-13-000

10/06

Data# Polling (DQ7)

When the SST29SF020/040 and SST29VF020/040

devices are in the internal Program operation, any

attempt to read DQ7 will produce the complement of the

true data. Once the Program operation is completed,

DQ7 will produce true data. Note that even though DQ7

may have valid data immediately following the completion

of an internal Write operation, the remaining data outputs

may still be invalid: valid data on the entire data bus will

appear in subsequent successive Read cycles after an

interval of 1 µs. During internal Erase operation, any

attempt to read DQ7 will produce a ‘0’. Once the internal

Erase operation is completed, DQ7 will produce a ‘1’. The

Data# Polling is valid after the rising edge of fourth WE#

(or CE#) pulse for Program operation. For Sector- or

Chip-Erase, the Data# Polling is valid after the rising

edge of sixth WE# (or CE#) pulse. See Figure 7 for

Data# Polling timing diagram and Figure 17 for a flow-

chart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating ‘0’s

and ‘1’s, i.e., toggling between 0 and 1. When the internal

Program or Erase operation is completed, the toggling will

stop. The device is then ready for the next operation. The

Toggle Bit is valid after the rising edge of fourth WE# (or

CE#) pulse for Program operation. For Sector or Chip-

Erase, the Toggle Bit is valid after the rising edge of sixth

WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing dia-

gram and Figure 17 for a flowchart.

Data Protection

The SST29SF020/040 and SST29VF020/040 devices

provide both hardware and software features to protect

nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5

ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 2.5V for SST29SF020/

040. The Write operation is inhibited when VDD is less than

1.5V. for SST29VF020/040.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the Write operation. This prevents inadvert-

ent writes during power-up or power-down.

Software Data Protection (SDP)

The SST29SF020/040 and SST29VF020/040 provide

the JEDEC approved Software Data Protection scheme for

all data alteration operations, i.e., Program and Erase. Any

Program operation requires the inclusion of a series of

three- byte sequence. The three-byte load sequence is

used to initiate the Program operation, providing optimal

protection from inadvertent Write operations, e.g., during

the system power-up or power-down. Any Erase operation

requires the inclusion of a six-byte load sequence. These

devices are shipped with the Software Data Protection per-

manently enabled. The specific software command codes

are shown in Table 4. During SDP command sequence,

invalid commands will abort the device to read mode, within

TRC.

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