November 1985

8

Philips Semiconductors

Product specification

Dual 16-bit DAC

TDA1541

* Signal-to-noise ratio

+ THD with 1 kHz full scale sinewave generated at a sampling rate of 176,4 kHz.

Signal -to-noise ratio + THD*

S/N

90

95

−

dB

Settling time to

± 1 LSB

−

1

−µs

Channel separation

α

80

tbf

−

dB

Unbalance between outputs

−

0,1

0,2

dB

Time delay between outputs

−−

1

µs

Power supply ripple rejection**

RR

−

tbf

−

dB

RR

−

tbf

−

dB

RR

−

tbf

−

dB

Signal-to-noise ratio

at bipolar zero

S/N

−−100

−

dB

Timing (see Figs 3, 4 and 5)

Rise time

−−

35

ns

Fall time

−−

35

ns

Bit clock cycle time

160

−−

ns

Bit clock HIGH time

48

−−

ns

Bit clock LOW time

48

−−

ns

Bit clock fall time to latch rise time

0

−−

ns

Bit clock rise time to latch fall time

0

−−

ns

Data set-up time to bit clock

32

−−

ns

Data hold time to bit clock

0

−−

ns

Data set-up time to system clock

32

−−

ns

Word select hold time to system clock

0

−−

ns

Word select set-up time to system clock

32

−−

ns

Bit clock fall time to system clock rise time

32

−−

ns

System clock rise time to bit clock fall time

32

−−

ns

System clock fall time to bit clock rise time

50

−−

ns

Bit clock rise time to system clock fall time

0

−−

ns

Latch enable LOW time

20

−−

ns

Latch enable HIGH time

32

−−

ns

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT