Rev. F

|

Page 14 of 38

|

November 2023

AD2426/AD2427/AD2428

Table 7. I2S Timing

1.8 V

3.3 V

Unit

Parameter

Min

Max

Min

Max

I

2S Slave Timing Requirements (A2B Main Node)

tBCLKW

BCLK Width

19.5

9.5

ns

tBCLKS

BCLK Period

39.0

19.0

ns

tSIS

1

SYNC Input Setup Before BCLK Sample Edge

2.25

2.25

ns

tSIH

1

SYNC Input Hold After BCLK Sample Edge

2.0

3.0

ns

tRISM

1

DRXn Input Setup Before BCLK Sample Edge

0.5

0.5

ns

tRIHM

1

DRXn Input Hold After BCLK Sample Edge

2.0

1.5

ns

tRISM

1, 2

DRX on DTX1 Input Setup Before BCLK Sample Edge

4.0

4.5

ns

tRIHM

1, 2

DRX on DTX1 Input Hold After BCLK Sample Edge

0.5

0.5

ns

I

2S Slave Switching Characteristics (A2B Main Node)

tDODM

3

DTXn Output Delay After BCLK Drive Edge

15.25

12.0

ns

tDOHM

3

DTXn Output Hold After BCLK Drive Edge

3.0

3.0

ns

tDOENM

3, 4

DTXn Data Enable Delay After BCLK Drive Edge

2.0

2.0

ns

tDODIM

3, 4

DTXn Data Disable Delay After BCLK Drive Edge

13.0

8.0

ns

I

2S Master Timing Requirements (A2B Subordinate Node)

tRISS

1

DRXn Input Setup Before BCLK Sample Edge

0.0

0.0

ns

tRIHS

1

DRXn Input Hold After BCLK Sample Edge

5.8

2.0

ns

tRISS

1, 2

DRX on DTX1 Input Setup Before BCLK Sample Edge

2.5

4.5

ns

tRIHS

1, 2

DRX on DTX1 Input Hold After BCLK Sample Edge

2.5

0.5

ns

I

2S Master Switching Characteristics (A2B Subordinate Node)

fBCLK

BCLK Output Frequency

5

25.0

50.0

MHz

tBCLKMOJ

BCLK Output Jitter (RMS Cycle to Cycle, fBCLK = 12.288 MHz)

100

100

ps

tSOL/tSOH

BCLK Duty Cycle

0.45

0.550.450.55tBCLK

tSOJ

SYNC Output Jitter (RMS Cycle to Cycle fSYNCM = 48 kHz)

2.2

2.2

ns

tSOD

3

SYNC Output Delay After BCLK Drive Edge

6.5

6.5

ns

tSOHD

3

SYNC Output Hold After BCLK Drive Edge

2.8

4.5

ns

tDODS

3

DTXn Output Delay After BCLK Drive Edge

10.8

9.25

ns

tDOHS

3

DTXn Output Hold After BCLK Drive Edge

5.5

6.0

ns

1 Referenced to sample edge.

2 The DTX1 pin can be configured as an I2S/TDM DRX pin using the I2SGCFG register.

3 Referenced to drive edge.

4 The DTXn pins can be tristated using the I2STXOFFSET register.

5 When VIOVDD = 3.3 V, the setup and hold timing at the 50 MHz maximum bit clock rate can be violated when interfacing with other I2S devices. The timing violations are seen

when the A2B subordinate node is receiving and the A2B main node is transmitting. In these modes, the maximum BCLK frequency of 50 MHz cannot be achieved.