PIC18F4520 datasheet(9/16 Pages) MICROCHIP

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DS80209D-page 9

PIC18F2420/2520/4420/4520

24. Module: EUSART

The EUSART auto-baud feature may periodically

measure the incoming baud rate incorrectly. The

rate of incorrect baud rate measurements will

depend on the frequency of the incoming

synchronization

byte

and

the

system

clock

frequency.

Work around

None.

25. Module: EUSART

In Synchronous mode (SYNC = 1) with clock

polarity high (SCKP = 1), the EUSART transmits a

shorter than expected clock on the CK pin for bit 0.

Work around

None.

26. Module: EUSART

In Synchronous mode, EUSART baud rates using

SPBRG values of ‘0’ and ‘1’ may not function

correctly.

Work around

Use another baud rate configuration to generate

the desired baud rate.

27. Module: MSSP

In an I2C™ system with multiple slave nodes, an

unaddressed slave may respond to bus activity

when data on the bus matches its address. The

first occurrence will set the BF bit. The second

occurrence will set the BF and SSPOV bits. In both

situations, the SSPIF bit is not set and an interrupt

will not occur. The device will vector to the Interrupt

Service Routine only if the interrupt is enabled and

an address match occurs.

Work around

The I2C slave must clear the SSPOV bit after each

I2C address match to maintain normal operation.

28. Module: MSSP

In I2C Master mode, the BRG value of ‘0’ may not

work correctly.

Work around

Use a BRG value greater than ‘0’ by setting

SSPADD

≥ 1.

29. Module: MSSP

In I2C Master mode, the RCEN bit is set by soft-

ware to begin data reception and cleared by the

peripheral after a byte is received. After a byte is

received, the device may take up to 80 TCY to clear

RCEN and 800 TCY when using MPLAB® ICD 2

and MPLAB ICE emulators.

Work around

Single byte receptions are typically not affected,

since the delay between byte receptions is

typically long enough for the RCEN bit to clear. For

multiple byte receptions, the software must wait

until the bit is cleared by the peripheral before the

next byte can be received.

30. Module: MSSP

Setting the SEN bit initiates a Start sequence on

the bus, after which, the SEN bit is cleared auto-

matically by hardware. If the SEN bit is set again

(without an address byte being transmitted), a

Start sequence will not commence and the SEN bit

will not be cleared. This condition causes the bus

to remain in an active state. The system is Idle

when ACKEN, RCEN, PEN, RSEN and SEN are

clear.

Work around

Set the PEN or RSEN bit to transmit a Stop or

Repeated Start sequence, although the SEN bit

may still be set, indicating the bus is active. After

the sequence has completed, the PEN, RSEN and

SEN bit will be clear, indicating the bus is Idle.

Clearing and setting the SSPEN bit will also reset

the I2C peripheral and clear the PEN, RSEN and

SEN status bits.

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