18F2420 datasheet(2/16 Pages) MICROCHIP

2 / 16 page

PIC18F2420/2520/4420/4520

DS80209D-page 2

Module: MSSP

When the MSSP is configured for SPI™ Master

mode, the SDO pin cannot be disabled by setting

the TRISC<5> bit. The SDO pin always outputs

the content of SSPBUF regardless of the state of

the TRIS bit.

In Slave mode with Slave Select enabled,

SSPM3:SSPM0 = 0010 (SSPCON1<3:0>), the

SDO pin can be disabled by placing a logic high

level on the SS pin (RA5).

Work around

None.

Date Codes that pertain to this issue:

All engineering and production devices.

Module: MSSP

After an I2C transfer is initiated, the SSPBUF

additional writes are blocked. The data transfer may

be corrupted if SSPBUF is written during this time.

The WCOL bit is set any time an SSPBUF write

occurs during a transfer.

Work around

Avoid writing SSPBUF until the data transfer is

complete, indicated by the setting of the SSPIF bit

(PIR1<3>).

Verify the WCOL bit (SSPCON1<7>) is clear after

writing SSPBUF to ensure any potential transfer in

progress is not corrupted.

Date Codes that pertain to this issue:

All engineering and production devices.

Module: MSSP

In 10-bit Addressing mode, when a Repeated Start

is issued, followed by the high address byte and a

write command (R/W = 0), an ACK is not issued.

Work around

There are two work arounds available:

1. Single-Master Environment:

In a single-master environment, the user must

issue a Stop, then a Start, followed by a write

to the address high, then the address low

followed by the data.

2. Multi-Master Environment:

In a multi-master environment, the user must

issue a Repeated Start, send a dummy write

command to a different address, issue another

Repeated Start and then send a write to the

original address. This procedure will help

maintain control of the bus.

Date Codes that pertain to this issue:

All engineering and production devices.

Module: MSSP

I2C Receive mode should be enabled (i.e., RCEN

bit should be set) only when the system is idle

(i.e., when ACKEN, RCEN, PEN, RSEN and SEN

all equal zero). It should not be possible to set the

RCEN bit when the system is not idle, however,

the RCEN bit can be set under this circumstance.

Work around

Wait for the system to become idle before setting the

RCEN bit. This requires a check for the following bits

to be clear:

ACKEN, RCEN, PEN, RSEN and SEN.

Date Codes that pertain to this issue:

All engineering and production devices.

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