AD9172-FMC-EBZ datasheet(49/146 Pages) AD

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Data Sheet

AD9172

JESD204B SERIAL DATA INTERFACE

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Rev. C | 49 of 146

Unexpected Control Character, NIT, Disparity

IRQs

For UEK character, NIT, and disparity errors, error count over the

threshold events are available as IRQ events. Enable these events

by writing to Register 0x4B8, Bits[7:5]. The IRQ event status can be

read at Register 0x4BA, Bits[7:5] after the IRQs are enabled.

See the Error Counter and IRQ Control section for information on

resetting the IRQ. See the Interrupt Request Operation section for

more information on IRQs.

Errors Requiring Reinitializing

A link reinitialization automatically occurs when four invalid disparity

characters or four NIT characters are received as per Section 7.1 of

the JESD204B specification. When a link reinitialization occurs, the

resync request is at least five frames and nine octets long.

The user can optionally reinitialize the link when the error count

for disparity errors, NIT errors, or UEK character errors reaches a

programmable error threshold. The process to enable the reinitiali-

zation feature for certain error types is as follows:

1. Choose and enable which errors to monitor by selecting them

in Register 0x480, Bits[5:3] to Register 0x487, Bits[5:3]. UEK,

BDE, and NIT error monitoring can be selected for each lane

by writing a 1 to the appropriate bit, as described in Table 33.

These are enabled by default.

2. Write a 0 to the corresponding bit to Register 0x480, Bits[2:0] to

3. Enable the sync assertion mask for each type of error by

writing to SYNC_ASSERT_MASK (Register 0x47D, Bits[2:0])

according to Table 33.

4. Program the desired error counter threshold into ER-

RORTHRES (Register 0x47C).

5. For each error type enabled in the SYNC_ASSERT_MASK reg-

ister, if the error counter on any lane reaches the programmed

threshold, SYNCOUTx± falls, issuing a sync request. Note that

all error counts are reset when a link reinitialization occurs. The

IRQ does not reset and must be reset manually.

Table 33. Sync Assertion Mask (SYNC_ASSERT_MASK)

Addr.

Bit No.

Bit Name

Description

0x47D

BDE

Set to 1 to assert SYNCOUTx± if

the disparity error count reaches the

threshold

NIT

Set to 1 to assert SYNCOUTx± if the

NIT error count reaches the threshold

UEK

Set to 1 to assert SYNCOUTx± if the

UEK character error count reaches

the threshold

CGS, Frame Sync, Checksum, and ILAS

Monitoring

each stage of the JESD204B link establishment has occurred.

Bit x of CODE_GRP_SYNC (Register 0x470) is high if Link Lane

x received at least four K28.5 characters and passed code group

synchronization.

Bit x of FRAME_SYNC (Register 0x471) is high if Link Lane x

completed initial frame synchronization.

Bit x of GOOD_CHECKSUM (Register 0x472) is high if the check-

sum sent over the lane matches the sum of the JESD204B parame-

ters sent over the lane during ILAS for Link Lane x. The parameters

can be added either by summing the individual fields in registers

or summing the packed register. The calculated checksums are the

lower eight bits of the sum of the following fields: DID, BID, LID,

SCR, L − 1, F − 1, K − 1, M − 1, N − 1, SUBCLASSV, NP − 1,

JESDV, S − 1, and HD.

Bit x of INIT_LANE_SYNC (Register 0x473) is high if Link Lane x

passed the initial lane alignment sequence.

CGS, Frame Sync, Checksum, and ILAS IRQs

Fail signals for CGS, frame sync, checksum, and ILAS are available

as IRQ events. Enable them by writing to Register 0x4B8, Bits[3:0].

The IRQ event status can be read at Register 0x4BA, Bits[3:0] after

the IRQs are enabled. Write a 1 to Register 0x4BA, Bit 0 to reset

the CGS IRQ. Write a 1 to Register 0x4BA, Bit 1 to reset the frame

sync IRQ. Write a 1 to Register 0x4BA, Bit 2 to reset the checksum

IRQ. Write a 1 to Register 0x4BA, Bit 3 to reset the ILAS IRQ.

See the Interrupt Request Operation section for more information.

Configuration Mismatch IRQ

The AD9172 has a configuration mismatch flag that is available as

an IRQ event. Use Register 0x4B9, Bit 0 to enable the mismatch

flag (it is enabled by default), and then use Register 0x4BB, Bit 0

to read back its status and reset the IRQ signal. See the Interrupt

Request Operation section for more information.

The configuration mismatch event flag is high when the link configu-

ration settings (in Register 0x450 to Register 0x45D) do not match

the JESD204B settings received by the device (Register 0x400 to

This function is different from the good checksum flags in Regis-

ter 0x472. The good checksum flags ensure that the transmitted

checksum matches a calculated checksum based on the transmit-

ted settings. The configuration mismatch event ensures that the

transmitted settings match the configured settings.

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