3

PS8765A

08/01/05

PI6C484321

260MHz Crystal-to-3.3V Differential

LVPECL Frequency Synthesizer

Pin Description

Number

Name

Type

Description

1

M5

Input

Pullup

M divider input. Data latched on LOW-to-HIGH transition of nP_

LOAD input. LVCMOS / LVTTL interface levels

2, 3, 4, 28,

29, 30, 31,

32

M6, M7, M8,

M0, M1, M2,

M3, M4

Input

Pulldown

5, 6

N0, N1

Input

Pulldown

Determines N output divider value as defined in Table 3C Function

table. LVCMOS / LVTTL interface levels

7

nc

unused

No connect

8, 16

Power

Negative supply pins

9

TEST

Output

Test output. ACTIVE in the serial mode of operation. Output driven

LOW in parallel mode. LVCMOS interface levels

10

Power

Positive supply pin

11, 12

FOUT1,

nFOUT2

Output

Differential output for the synthesizer. LVPECL interface levels

13

Power

Output supply pin

14, 15

FOUT0,

nFOUT0

Output

Differential output for the synthesizer. LVPECL interface levels

17

MR

Input

Pulldown

Active High Master reset. When logic HIGH, the internal dividers are

reset causing the true outputs FOUTx to go low and the inverted out-

puts nFOUTx to go high. When logic LOW, the internal dividers and

the outputs are enabled. Assertion of MR does not affect loaded M, N,

and T values. LVCMOS / LVTTL interface levels.

18

S_CLOCK

Input

Pulldown

Clocks in serial data present at S_DATA input into the shift register on

the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.

19

S_DATA

Input

Pulldown

Shirft register serial input. Data sampled on the rising edge of

S_CLOCK. LVCMOS / LVTTL interface levels.

20

S_LOAD

Input

Pulldown

Control transition of data from shift register into the dividers.

LVCMOS / LVTTL interface levels

21

Power

Analog supply pin

22

XTAL_SEL

Input

Pullup

Selects between crystals or test inputs as the PLL reference source.

Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.

LVCMOS / LVTTL interface levels.

23

TEST_CLK

Input

Pulldown

Test clock input. LVCMOS / LVTTL interface levels

24, 25

XTAL1, XTAL2

Input

Crystal oscillator inputs

26

nP_LOAD

Input

Pulldown

Parallel load input to determine when data present at M8:M0 is loaded

into M divider, and when data is present at N1:N0 sets the N output

divider value. LVCMOS / LVTTL interface levels.

27

VCO_SEL

Input

Pullup

Controls the clock synthesizer to be in PLL or bypass mode.

LVCMOS /LVTTL interface levels

Notes

1.

Pullup and Pulldown refer to internal input resistors. See Pin characterstics Table for typical values.