TDA5153 datasheet(13/28 Pages) PHILIPS

13 / 28 page

1997 Jul 02

Philips Semiconductors

Preliminary speciﬁcation

Pre-ampliﬁer for Hard Disk Drive (HDD)

with MR-read/inductive write heads

TDA5153

8.10

Operation of the serial interface

8.10.1

CONFIGURATION

By default (d0 = logic 0), write data passes from the

write data input via the data flip-flop to the write driver.

The write driver toggles the current in the head at the

falling edges of

When d0 = logic 1, the flip-flop is not used. The signal

polarity is non-inverting from WDIx and WDIy to Wx and

Wy.

By default (d1 = logic 0) the pre-amplifier senses PECL

write signals at WDIx and WDIy. d1 should remain

logic 0.

By default, (d2 = logic 0) the write current is inhibited

under low supply voltage conditions. The write current

inhibit is made inactive by programming d2 to logic 1.

By default (d3 = logic 0), in write mode low supply

voltage, open head, and other conditions are monitored

and flagged at HUS. If d3 = logic 1, HUS is LOW in write

mode and HIGH in read mode.

The amplifier read gain may be programmed in the

configuration register. By default (d4 = logic 0), the read

gain is typically 160 with RMR =28 Ω. If d4 = logic 1, the

read amplifier typical gain is 3 dB higher (i.e. 226 if

RMR =28 Ω).

In order to minimize the write-to-read recovery times,

the first stage of the read amplifier may be kept biased

during write mode. By default, (d5 = logic 0) the read

amplifier is powered-down during write mode, and the

fast settling procedure is activated after write-to-read

switching. If d5 = logic 1 the read amplifier is kept biased

during write mode, and the fast settling procedure still

occurs if the head is changed or the MR current is

re-programmed.

8.10.2

POWER CONTROL

By default d0 = d1 = logic 0, the pre-amplifier powers-up in

sleep mode. If d1 = logic 0, d0 = logic 1 or d1 = logic 1,

d0 = logic 0 the circuit goes in standby mode.

data

WDIx

WDIy

–

--------------------------------------

If d1 = d0 = logic 1, the circuit goes in active mode, (read

or write mode depending on the R/W input).

8.10.3

HEAD SELECT

d2, d1 and d0 are used to select head H0 to H5 for the

6 channel version and to select head H1 to H4 for the

4 channel version.

8.10.4

SERVO WRITE

The circuit is prepared for servo writing. However, the chip

will not be guaranteed.

8.10.5

TEST

d2 = d1 = d0 = logic 0. The circuit is not in test mode. This

is the default situation.

8.10.5.1

MR head test

d2 = logic 0, d1 = logic 0, d0 = logic 1. In read mode, the

voltages at Rx and Ry (at the top of the MR elements) of

the selected head are fed to RDx and RDy outputs. By

measuring the output voltages single-ended at two

different IMR currents, the MR resistance can be accurately

measured according to the following formula:

for the x side for instance.

Open head and head short-circuited to ground conditions

can therefore be detected.

d2 = logic 0, d1 = logic 1, d0 = logic 0. Same as before,

with the difference that IMR2 is fixed to a minimum constant

value of 5 mA. Measuring in the same way as above with

IMR1 > 5 mA, enables the detection of MR elements

connected together.

8.10.5.2

Temperature monitor

d2 = logic 0, d1 = logic 1, d0 = logic 1. The temperature

monitor voltages are connected to RDx and RDy. The

output differential voltage depends on the temperature

according to:

The temperature may be measured with a typical precision

of 5

°C.

MRx

RDx1

RDx2

–

MRx1

MRx2

–

---------------------------------------

0.00364

–

1.7

140

°C

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