POWR6AT6 datasheet(21/34 Pages) LATTICE

21 / 34 page

Lattice Semiconductor

ispPAC-POWR6AT6 Data Sheet

Writing a value to the ADC_MUX register to set the input attenuator and selector will automatically initiate a conver-

sion. When the conversion is in process, the DONE bit (ADC_VALUE_LOW.0) will be reset to 0. When the conver-

sion is complete, this bit will be set to 1. When the conversion is complete, the result may be read out of the ADC by

performing two I

2C read operations; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH. It is recom-

mended that the I

2C master load a second conversion command only after the completion of the current conversion

command (Waiting for the DONE bit to be set to 1). An alternative would be to wait for a minimum speciﬁed time

(see Tconvert value in the speciﬁcations) and disregard checking the DONE bit.

Note that if the I

2C clock rate falls below 50kHz (see FI2C note in speciﬁcations), the only way to insure a valid ADC

conversion is to wait the minimum speciﬁed time (Tconvert), as the operation of the DONE bit at clock rates lower

than that cannot be guaranteed. In other words, if the I

2C clock rate is less than 50kHz, the DONE bit may or may

not assert even when a valid conversion result is available. Erroneous ADC readout results are also possible when-

ever the I

2C clock is less than 50kHz and a second ADC convert is commanded before a full TCONVERT time period

has elapsed. Under these conditions, it is still possible to obtain valid results for the second conversion by reading

out the ADC low and high byte results twice in succession (read ADC_VALUE_LOW, read ADC_VALUE_HIGH,

then repeating the low and high byte reads). Only the second ADC readout value is reliably valid, however.

To insure every ADC conversion result is valid, preferred operation is to clock I

2C at more than 50kHz and verify

DONE bit status or wait for the full TCONVERT time period between subsequent ADC convert commands. If an I

request is placed before the current conversion is complete, the DONE bit will be set to 1 only after the second

request is complete.

The UES word may also be read through the I

2C interface, with the register mapping shown in Figure 17.

Figure 17. I

2C Register Mapping for UES Bits

The I

2C interface also provides the ability to initiate reset operations. The ispPAC-POWR6AT6 may be reset by issu-

ing a write of any value to the I

2C RESET register (Figure 18). Refer to the RESET Command via JTAG or I2C sec-

tion of this data sheet for further information.

UES7

UES6

UES5

UES4

UES3

UES2

UES1

UES0

0x04 - UES_BYTE0

(Read Only)

UES15

UES14

UES13

UES12

UES11

UES10

UES9

UES8

0x05 - UES_BYTE1

(Read Only)

UES23

UES22

UES21

UES20

UES19

UES18

UES17

UES16

0x06 - UES_BYTE2

(Read Only)

UES31

UES30

UES29

UES28

UES27

UES26

UES25

UES24

0x07 - UES_BYTE3

(Read Only)

POWR6AT6 Datasheet(PDF) 21 Page - Lattice Semiconductor

POWR6AT6 Datasheet(HTML) 21 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL