NAND512R3A2C datasheet(11/51 Pages) STMICROELECTRONICS

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NAND512-A2C

Memory array organization

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Memory array organization

The memory array is made up of NAND structures where 16 cells are connected in series.

The memory array is organized in blocks where each block contains 32 pages. The array is

split into two areas, the main area and the spare area. The main area of the array is used to

store data whereas the spare area is typically used to store Error correction Codes, software

flags or Bad Block identification.

In x8 devices the pages are split into a main area with two half pages of 256 Bytes each and

a spare area of 16 Bytes. In the x16 devices the pages are split into a 256 Word main area

and an 8 Word spare area. Refer to Figure 5: Memory array organization.

Bad blocks

The NAND Flash 528 Byte/ 264 Word Page devices may contain Bad Blocks, that is blocks

that contain one or more invalid bits whose reliability is not guaranteed. Additional Bad

Blocks may develop during the lifetime of the device.

The Bad Block Information is written prior to shipping (refer to Section 7.1: Bad Block

management for more details).

Table 4 shows the minimum number of valid blocks in each device. The values shown

include both the Bad Blocks that are present when the device is shipped and the Bad Blocks

that could develop later on.

These blocks need to be managed using Bad Blocks Management, Block Replacement or

Error Correction Codes (refer to Section 7: Software algorithms).

Table 4.

Valid blocks

Density of Device

Min

Max

512Mbits

4016

4096

NAND512R3A2C Datasheet(PDF) 11 Page - STMicroelectronics