STM32F101R6 datasheet(54/64 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F101xx

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5.3.16

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 37 are derived from tests

performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage

conditions summarized in Table 7.

Note:

It is recommended to perform a calibration after each power-up.

Table 37.

ADC characteristics(1)

TBD = to be determined.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDDA

ADC power supply

2.4

3.6

VREF+

Positive reference voltage

2.0

VDDA

fADC

ADC clock frequency

0.6

MHz

Sampling rate

TBD

0.05

MHz

fTRIG

External trigger frequency

fADC = 14 MHz

823

kHz

1/fADC

VAIN

Conversion voltage range 2)

VSSA

VDDA

RAIN

External input impedance

TBD(2)(3)

Depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and reduced to

allow the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤14 MHz.

During the sample time the input capacitance CAIN (5 max) can be charged/discharged by the external

source. The internal resistance of the analog source must allow the capacitance to reach its final voltage

level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on

the conversion result. Values for the sample clock tS depend on programming.

Ω

CAIN

External capacitor on analog

input

Ilkg

Negative input leakage current on

analog pins

VIN < VSS, | IIN |<

400 µA on adjacent

analog pin

µA

RADC

Sampling switch resistance

Ω

CADC

Internal sample and hold

capacitor

5pF

tCAL

Calibration time

fADC = 14 MHz

5.9

µs

1/fADC

tlat

Injection conversion latency

fADC = 14 MHz

0.214

µs

31/fADC

Sampling time

fADC = 14 MHz

0.107

17.1

µs

tSTAB

Power-up time

µs

tCONV

Total conversion time (including

sampling time)

fADC = 14 MHz

118

µs

14 (1.5 for sampling

+12.5 for successive

approximation)

1/fADC

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