Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

TSA1204 Datasheet(PDF) 6 Page - STMicroelectronics

Part # TSA1204
Description  Dual channel 12-bit 20Msps 120mW A/D converter
PDF  31 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

TSA1204 Datasheet(HTML) 6 Page - STMicroelectronics

Back Button TSA1204_06 Datasheet HTML 2Page - STMicroelectronics TSA1204_06 Datasheet HTML 3Page - STMicroelectronics TSA1204_06 Datasheet HTML 4Page - STMicroelectronics TSA1204_06 Datasheet HTML 5Page - STMicroelectronics TSA1204_06 Datasheet HTML 6Page - STMicroelectronics TSA1204_06 Datasheet HTML 7Page - STMicroelectronics TSA1204_06 Datasheet HTML 8Page - STMicroelectronics TSA1204_06 Datasheet HTML 9Page - STMicroelectronics TSA1204_06 Datasheet HTML 10Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 31 page
background image
Dynamic characteristics
TSA1204
6/31
3
Dynamic characteristics
Dynamic characteristics are measured at AVCC = DVCC = VCCB = 2.5 V, FS= 20 Msps,
Fin=10.5 MHz, Vin@ -1 dBFS, VREFP=1.0 V, VREFM=0 V and Tamb = 25° C (unless otherwise
specified).
4
Timing characteristics
Timing characteristics are measured at AVCC = DVCC = VCCB = 2.5 V, FS= 20 Msps,
Fin=10.5 MHz, Vin@ -1 dBFS, VREFP=1.0 V, VREFM=0 V and Tamb = 25° C (unless otherwise
specified).
Table 2.
Dynamic characteristics
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
SFDR
Spurious free dynamic range
-81.5
-71.0
dBc
SNR
Signal to noise ratio
66.9
68.5
dB
THD
Total harmonics distortion
-80
-70
dBc
SINAD
Signal to noise and distortion ratio
64.8
68
dB
ENOB
Effective number of bits
10.6
11.2
bits
Table 3.
Timing characteristics
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
FS
Sampling frequency
0.5
20
MHz
DC
Clock duty cycle
45
50
55
%
TC1
Clock pulse width (high)
22.5
25
ns
TC2
Clock pulse width (low)
22.5
25
ns
Tod
Data output delay (clock edge to data
valid)
10 pF load
capacitance
9ns
Tpd I
Data pipeline delay for channel I
7
cycle
s
Tpd Q
Data pipeline delay for channel Q
7.5
cycle
s
Ton
Falling edge of OEB to digital output
valid data
1ns
Toff
Rising edge of OEB to digital output
tri-state
1ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com