STM8L052R8 datasheet(7/109 Pages) STMICROELECTRONICS

7 / 109 page

STM8L052R8

List of figures

Doc ID023337 Rev 2

7/109

List of figures

Figure 1.

High density value line STM8L05xxx device block diagram

. . . . . . . . . . . . . . . . . . . . . . 12

Figure 2.

High density value line STM8L05xxx clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3.

STM8L052R8 64-pin LQFP64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 4.

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 5.

Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 6.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 7.

Power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 8.

Typical IDD(RUN) from RAM vs. VDD (HSI clock source), fCPU =16 MHz

1) . . . . . . . . . . . . . 64

Figure 9.

Typical IDD(RUN) from Flash vs. VDD (HSI clock source), fCPU = 16 MHz

1) . . . . . . . . . . . . 64

Figure 10.

Typical IDD(Wait) from RAM vs. VDD (HSI clock source), fCPU = 16 MHz

1) . . . . . . . . . . . . . 66

Figure 11.

Typical IDD(Wait) from Flash (HSI clock source), fCPU = 16 MHz

1) . . . . . . . . . . . . . . . . . . . 66

Figure 12.

Typical IDD(LPR) vs. VDD (LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . . 68

Figure 13.

Typical IDD(LPW) vs. VDD (LSI clock source), all peripherals OFF

(1) . . . . . . . . . . . . . . . . . 69

Figure 14.

Typical IDD(AH) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 15.

Typical IDD(Halt) vs. VDD (internal reference voltage OFF) . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 16.

HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 17.

LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 18.

Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 19.

Typical LSI clock source frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 20.

Typical VIL and VIH vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 21.

Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 22.

Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 23.

Typical pull-up current Ipu vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 24.

Typical VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 25.

Typical VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 26.

Typical VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 27.

Typical VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 28.

Typical VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 29.

Typical VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 30.

Typical NRST pull-up resistance RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 31.

Typical NRST pull-up current Ipu vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 32.

Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 33.

SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 34.

SPI1 timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 35.

SPI1 timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 36.

Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 37.

ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 38.

Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 39.

Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 100

Figure 40.

Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . 100

Figure 41.

LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 105

Figure 42.

Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 43.

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

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