 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
25LC040AX-I/ST Datasheet(PDF) 7 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
25LC040AX-I/ST Datasheet(HTML) 7 Page - Microchip Technology |
|
|
7 / 28 page  © 2007 Microchip Technology Inc. DS21827D-page 7 25AA040A/25LC040A BLOCK DIAGRAM FIGURE 2-1: READ SEQUENCE SI SO SCK CS HOLD WP STATUS Register I/O Control Memory Control Logic X Dec HV Generator EEPROM Array Page Latches Y Decoder Sense Amp. R/W Control Logic VCC VSS TABLE 2-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 A8011 Read data from memory array beginning at selected address WRITE 0000 A8010 Write data to memory array beginning at selected address WRDI 0000 x100 Reset the write enable latch (disable write operations) WREN 0000 x110 Set the write enable latch (enable write operations) RDSR 0000 x101 Read STATUS register WRSR 0000 x001 Write STATUS register Note: A8 is the 9th address bit, which is used to address the entire 512 byte array. x = don’t care. SO SI SCK CS 0 2345 6789 10 11 1 01 A8 0 0 0 01 A7 A6 A5 A4 A1 A0 76543210 Data Out High-impedance A3 A2 Lower Address Byte 12 13 14 15 16 17 18 19 20 21 22 23 Instruction+Address MSb |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
