MCP9805

DS21977B-page 12

© 2005 Microchip Technology Inc.

bit 6

0

1

When enabled, this bit remains set ‘1’ or locked until cleared by internal reset (Section 4.3 “Summary of

Power-up Default”). This bit does not require a double-write.

bit 5

Interrupt Clear (Int. Clear) bit:

0

= No effect. (power-up default)

1

= Clear interrupt output. When read this bit returns ‘0’.

bit 4

Event Output Status (Event Stat.) bit:

0

= Event output is not asserted by the device. (power-up default)

1

= Event output is asserted as a comparator/interrupt or critical temperature output.

bit 3

Event Output Control (Event Cnt.) bit:

0

= Disabled. (power-up default)

1

= Enabled.

This bit can not be altered when either of the lock bits is set (bit 6 and bit 7).

bit 2

Event Output Select (Event Sel.) bit:

0

1

When the Alarm Window Lock bit is set ‘1’ (bit 6), this bit cannot be altered until unlocked.

bit 1

Event Output Polarity (Event Pol.) bit:

0

= Active-low. (power-up default)

1

= Active-high.

This bit cannot be altered when either of the lock bits is set (bit 6 and bit 7).

bit 0

Event Output Mode (Event Mod.) bit:

0

= Comparator output. (power-up default)

1

= Interrupt output.

This bit cannot be altered when either of the lock bits is set (bit 6 and bit 7).

REGISTER 4-3:

CONFIGURATION REGISTER (CONFIG)

→ ADDRESS ‘0000 0001’b

(CONTINUED)

.

Upper-Half:

U-0

U-0

U-0

U-0

U-0

R/W-0

R/W-0

R/W-0

——

—

—

—

SHDN

bit 15

bit 8

Lower-Half:

R/W-0

R/W-0

R/W-0

R-0

R/W-0

R/W-0

R/W-0

R/W-0

Crit. Lock

Win. Lock

Int. Clear

Event Stat. Event Cnt.

Event

Sel.

Event

Pol.

Event

Mod.

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown