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24LC128-I/ST Datasheet(PDF) 16 Page - Microchip Technology |
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24LC128-I/ST Datasheet(HTML) 16 Page - Microchip Technology |
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16 / 42 page ![]() 24AAXX/24LCXX/24FCXX DS21930B-page 16 © 2007 Microchip Technology Inc. 6.0 WRITE OPERATIONS 6.1 Byte Write A byte write operation begins with a Start condition from the master followed by the four-bit control code (see Figure 6-1 and Figure 6-2). The next 3 bits are either the Block Address bits (for devices without address pins) or the Chip Select bits (for devices with address pins). Then the master transmitter clocks the R/W bit (which is a logic low) onto the bus. The slave then generates an Acknowledge bit during the ninth clock cycle. The next byte transmitted by the master is the address byte (for 128-bit to 16 Kbit devices) or the high-order address byte (for 32-512 Kbit devices). For 32 through 512 Kbit devices, the high-order address byte is followed by the low-order address byte. In either case, each address byte is acknowledged by the 24XX and the address bits are latched into the internal address counter of the 24XX. For the 24XX00 devices, only the lower four address bits are used by the device. The upper four bits are “don’t cares.” After receiving the ACK from the 24XX acknowledging the final address byte, the master device transmits the data word to be written into the addressed memory location. The 24XX acknowledges again and the master generates a Stop condition, which initiates the internal write cycle. If an attempt is made to write to an array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written, and the device will immediately accept a new command. After a byte Write command, the internal address counter will increment to the next address location. During a write cycle, the 24XX will not acknowledge commands. FIGURE 6-1: BYTE WRITE: 128-BIT TO 16 KBIT DEVICES FIGURE 6-2: BYTE WRITE: 32 TO 512 KBIT DEVICES S P Bus Activity Master SDA Line Bus Activity S T A R T S T O P Control Byte Address Byte Data A C K A C K A C K Byte Bus Activity Master SDA Line Bus Activity S T A R T Control Byte High Order Address Byte Low Order Address Byte Data S T O P A C K A C K A C K A C K S P Byte |
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