TDA8752B datasheet(3/36 Pages) PHILIPS

3 / 36 page

2000 Jan 10

Philips Semiconductors

Preliminary speciﬁcation

Triple high-speed Analog-to-Digital

Converter 110 Msps (ADC)

TDA8752B

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

VCCA

analog supply voltage

for R, G and B channels

4.75

5.0

5.25

VDDD

logic supply voltage

for I2C-bus and 3-wire

4.75

5.0

5.25

VCCD

digital supply voltage

4.75

5.0

5.25

VCCO

output stages supply voltage

for R, G and B channels

4.75

5.0

5.25

VCCA(PLL)

analog PLL supply voltage

4.75

5.0

5.25

VCCO(PLL)

output PLL supply voltage

4.75

5.0

5.25

ICCA

analog supply current

−

120

−

IDDD

logic supply current

for I2C-bus and 3-wire

−

1.0

−

ICCD

digital supply current

−

ICCO

output stages supply current

fCLK = 110 MHz;

ramp input

−

ICCA(PLL)

analog PLL supply current

−

ICCO(PLL)

output PLL supply current

−

fCLK

maximum clock frequency

TDA8752B/8

110

−−

MHz

fref(PLL)

PLL reference clock frequency

−

280

kHz

fVCO

VCO output clock frequency

−

110

MHz

INL

DC integral non linearity

from analog input to

digital output; full-scale;

ramp input;

fCLK = 110 MHz

−±0.5

±1.5

LSB

DNL

DC differential non linearity

from analog input to

digital output; full-scale;

ramp input;

fCLK = 110 MHz

−±0.5

±1.0

LSB

∆G

amp/T

ampliﬁer gain stability as a function of

temperature

Vref = 2.5 V with

100 ppm/

°C maximum

−−

200

ppm/

°C

ampliﬁer bandwidth

−3 dB; Tamb =25 °C

250

−−

MHz

tset

settling time of the ADC block plus AGC

input signal settling

time < 1 ns; Tamb =25 °C

−−

6ns

DRPLL

PLL divider ratio

100

−

4095

Ptot

total power consumption

fCLK = 110 MHz;

ramp input

−

1.1

−

jPLL(rms)

maximum PLL phase jitter (RMS value)

fref = 66.67 kHz;

fCLK = 110 MHz

−

0.67

−

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