TDA8768 datasheet(8/20 Pages) PHILIPS

8 / 20 page

1998 Aug 26

Philips Semiconductors

Preliminary speciﬁcation

12-bit high-speed Analog-to-Digital

Converter (ADC)

TDA8768

Voltage controlled regulator input Vref (referenced to AGND); note 2

Vref(FS)

full-scale ﬁxed voltage

VCCA =5V

−

3.175

−

Iref

input current

−

0.5

µA

VI(p-p) − VI(p-p) input voltage amplitude

(peak-to-peak value)

Vref =VCCA − 1.825 V

−

2.0

−

Outputs (referenced to OGND)

DIGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO OGND)

VOL

LOW-level output voltage

IOL = 2 mA

−

0.5

VOH

HIGH-level output voltage

IOH = −0.4 mA

VCCO − 0.5

−

VCCO

output current in 3-state

output level between 0.5 V

and VCCO

−20

−

+20

µA

Switching characteristics

CLOCK FREQUENCY fCLK; see Fig.3

fCLK(min)

minimum clock frequency

SH = HIGH

−−

MHz

fCLK(max)

maximum clock frequency

TDA8768H/4

−−

MHz

TDA8768H/5

−−

MHz

tCLKH

clock pulse width HIGH

8.5

−−

tCLKL

clock pulse width LOW

8.5

−−

Analog signal processing; 50% clock duty factor; VI − VI = 2.0 V; Vref =VCCA − 1.825 V; see Table 1

LINEARITY

INL

integral non-linearity

fCLK = 4 MHz; fi = 400 kHz

−±2.0

±4.5

LSB

DNL

differential non-linearity

fCLK = 4 MHz; fi = 400 kHz;

no missing code

−±0.6

±1.0

LSB

Eoffset

offset error

VCCA =VCCD =VCCO =5V;

Tamb =25 °C; VI = VI;

output code = 2047

tbf

−11

tbf

EG(FS)

gain error amplitude

(full scale); spread from

device to device

VCCA =VCCD =VCCO =5V;

Tamb =25 °C;

VI(p-p) − VI(p-p) = 2.0 V

−5

−

BANDWIDTH (fCLK = 55 MHz); note 3

analog bandwidth

−3 dB; full scale input

tbf

190

−

MHz

HARMONICS (fCLK = 40 MHz)

hfund(FS)

fundamental harmonics

(full scale)

fi = 4.43 MHz

−−

0dB

htot(FS)

harmonics (full scale);

all components

fi = 4.43 MHz

second harmonic

−−75

−

third harmonic

−−70

−

THD

total harmonic distortion

fi = 4.43 MHz; note 4

−−66

−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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