M30302SPGP datasheet(15/57 Pages) RENESAS

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M16C/30P Group

2. Central Processing Unit (CPU)

Rev.1.22

Mar 30, 2007

Page 15 of 53

REJ03B0088-0122

2.2

Address Registers (A0 and A1)

The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative

addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.

In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).

2.3

Frame Base Register (FB)

FB is configured with 16 bits, and is used for FB relative addressing.

2.4

Interrupt Table Register (INTB)

INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

2.5

Program Counter (PC)

PC is configured with 20 bits, indicating the address of an instruction to be executed.

2.6

User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.

Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.

2.7

Static Base Register (SB)

SB is configured with 16 bits, and is used for SB relative addressing.

2.8

Flag Register (FLG)

FLG consists of 11 bits, indicating the CPU status.

2.8.1

Carry Flag (C Flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

2.8.2

Debug Flag (D Flag)

The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.

2.8.3

Zero Flag (Z Flag)

This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.

2.8.4

Sign Flag (S Flag)

This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.

2.8.5

2.8.6

Overflow Flag (O Flag)

This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.

2.8.7

Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt.

Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag

is cleared to “0” when the interrupt request is accepted.

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