M62021FP datasheet(8/14 Pages) RENESAS

8 / 14 page

M62021L/P/FP

REJ03D0784-0200 Rev.2.00 Jun 15, 2007

Page 8 of 13

Timing Chart

V1 = VIN – VDROP

V2 = VIN – Q4VEB(Di)

V3 = VIN(VSL) – VDROP

V4 = VIN(VSL) – Q4VEB(Di)

V5 = VBAT – VF

∆VS

VSH

VIN(VSL)

VOH(RES)

VOL(RES)

VOL(CS)

VOL(RES)

VSL

tpd

RES

VOUT

VIN

Figure 6 Timing Chart

In Normal Operation

In Failure (Instantaneous

Drop)

Restoration from Failure

(Instantaneous Drop)

In Backup State

Input

Voltage

Output

Input voltage: 5V

→4V

Each output varies if the input

voltage drops to VSL or under

Input voltage: 4V

→5V

If the input voltage goes higher

than VSL by 100mV, each

output varies after delay

produced by the delay circuit

Input voltage: 0V

Backup voltage: 3V

VOUT

With Q4 set to ON,

a voltage (VIN – VDROP)

is output

Q4 is turned OFF. A voltage

(VIN – Q4VEB(Di)) is output by

the diode between E and B of

Q4.

Q4 is turned ON after delay

and a voltage (VIN – VDROP) is

output.

VBAT – VF

RES

The output level is VOL

(

RES) with a logic low

As the state shifts from a logic

low to logic high, the output

level becomes approximately

equal to the input voltage.

A logic high is maintained, and

than shifts to a logic high.

—

RES

The output level is VOH

(

RES) with a logic low

As the state shifts from a logic

high to logic low, the output

level becomes VOL (RES).

A logic low is held, and than

shifts to a logic high.

—

The output level is VOL

(

CS) with a logic low

As the state shifts from a logic

low to logic high, the output

level becomes the voltage VIN –

Q4VEB(Di).

A logic high is maintained, and

than shifts to a logic high.

The output is a logic

high and the output

level is VBAT – VF

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