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M58LT256JST Datasheet(PDF) 1 Page - STMicroelectronics |
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M58LT256JST Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 106 page ![]() June 2007 Rev 2 1/106 1 M58LT256JST M58LT256JSB 256 Mbit (16 Mb × 16, multiple bank, multilevel, burst) 1.8 V supply, secure Flash memories Features ■ Supply voltage –VDD = 1.7 V to 2.0 V for program, erase and read –VDDQ = 2.7 V to 3.6 V for I/O Buffers –VPP = 9 V for fast program ■ Synchronous / Asynchronous Read – Synchronous Burst Read mode: 52 MHz – Random access: 85 ns – Asynchronous Page Read mode ■ Synchronous Burst Read Suspend ■ Programming time – 5 µs typical Word program time using Buffer Enhanced Factory Program command ■ Memory organization – Multiple Bank memory array: 16 Mbit banks – Parameter Blocks (top or bottom location) ■ Dual operations – program/erase in one Bank while read in others – No delay between read and write operations ■ Block protection – All blocks protected at Power-up – Any combination of blocks can be protected with zero latency – Absolute Write Protection with VPP = VSS ■ Security – Software security features – 64 bit unique device number – 2112 bit user programmable OTP Cells ■ Common Flash Interface (CFI) ■ 100 000 program/erase cycles per block ■ Electronic signature – Manufacturer Code: 20h – Top Device Codes: M58LT256JST: 885Eh – Bottom Device Codes M58LT256JSB: 885Fh ■ TBGA64 package – ECOPACK® compliant TBGA64 (ZA) 10 x 13 mm BGA www.st.com |
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