TDA9964 datasheet(8/24 Pages) PHILIPS

8 / 24 page

2000 May 02

Philips Semiconductors

Objective speciﬁcation

12-bit, 3.0 V, 30 Msps analog-to-digital

interface for CCD cameras

TDA9964

Total chain characteristics (CDS + PGA + ADC)

fpix(max)

maximum pixel frequency

−−

MHz

fpix(min)

minimum pixel frequency

tbf

−−

MHz

tCLKH

CLK pulse width HIGH

−−

tCLKL

CLK pulse width LOW

−−

td(SHD;CLK)

time delay between

SHD and CLK

see Figs 3 and 4

−−

tsu(BLK;SHD)

set-up time of BLK compared

to SHD

see Figs 3 and 4

−−

Vi(IN)

video input dynamic signal

for ADC full-scale output

PGA code = 00

800

−−

PGA code = 255

−−

Ntot(rms)

total noise from CDS input to

ADC output (RMS value)

see Fig.8

PGA gain = 0 dB

−

1.5

−

LSB

PGA gain = 9 dB

−

2.2

−

LSB

Ein(rms)

equivalent input noise

voltage (RMS value)

PGA gain = 24 dB

−

−µV

PGA gain = 9 dB

−

140

−µV

OCCD(max)

maximum offset between

CCD ﬂoating level and CCD

dark pixel level

−100

−

+100

Digital-to-analog converter (OFDOUT DAC)

VOFDOUT(p-p) additional 8-bit control DAC

(OFD) output voltage

(peak-to-peak value)

Ri =1MΩ−

1.0

−

VOFDOUT(0)

DC output voltage for code 0

−

AGND

−

VOFDOUT(255) DC output voltage for

code 255

−

AGND + 1.0

−

TCDAC

DAC output range

temperature coefﬁcient

−

250

−

ppm/

°C

ZOFDOUT

DAC output impedance

−

2000

−Ω

IOFDOUT

OFD output current drive

static

−−

100

µA

Digital outputs (fpix = 30 MHz; CL = 10 pF); see Figs 3 and 4

VOH

HIGH-level output voltage

IOH = −1mA

VCCO − 0.5 −

VCCO V

VOL

LOW-level output voltage

IOL = 1 mA

−

0.5

IOZ

output current in 3-state

mode

0.5V<Vo <VCCO

−20

−

+20

µA

th(o)

output hold time

−−

td(o)

output delay time

CL = 10 pF; VCCO = 3.0 V

−

tbf

CL = 10 pF; VCCO = 2.7 V

−

tbf

output load capacitance

−−

Serial interface

fSCLK(max)

maximum frequency of serial

interface

−−

MHz

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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