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PT0239L (06/07)

Ver: 0

3

Data Sheet

PT7C4050

PLL with Integrated VCXO

Pin Description

Pin

Sym

Description

1

X1

Crystal oscillator connected between X1 and X2

2

VC

Control voltage input. It controls crystal oscillator (VCXO).

3

NC

Not connected.

4

AGND

Analog ground.

5

OPN

Negative input. terminal to internal operational amplifier.

6

OPOUT

Output. terminal of internal operational amplifier.

7

OPP

Positive input. terminal to internal operational amplifier.

8

S1

9

S2

10

S3

S1, S2, S3 Options for selectable divider N

11

LOS-IN1

(LOSIN)

TTL input. Internal pull down. Normally this pin is connected to OUT1 and selects REF-CLK1

input

12

PHO

Output. signal produced by phase detector of data.

13

REF-CLK1

(DATAIN)

Input clock signal. to phase detector

(TTL switching thresholds for recovering DATAIN)

14

FB-CLK

(CLKIN)

TTL switching thresholds input. Connected to external feedback clock.

15

DGND

Digital ground.

16

LOS

Loss of signal detection. for DATAIN input. Refer to LOS detection description.

17

RCLK

(CLK-OUT3)

Output recovered clock.

18

RDATA

(CLK-OUT4)

Output recovered data stream.

19

DVDD

Digital power supply.

CLK-OUT2

Output clock of internal VCXO frequency controlled by S3, S2, S1 while S4 set logic high

21

HIZ

TTL input. When set to a logic low, output pins CLK-OUT1, CLK-OUT2, RCLK, and RDATA

buffers are set to high-impedance state. When set to logic high or no connection, the device

functions and output pins CLK-OUT1, CLK-OUT2, RCLK, and RDATA etc. are active. This input

has an internal pull-up resistor.

22

CLK-OUT1

Output clock. of internal VCXO or half VCXO frequency, controlled by SEL-OUT1.

SEL-OUT1

CMOS input. ‘LO’ selects half of internal VCO frequency. ‘HI’ selects internal VCO frequency.

Internal pull up.

24

GND

Ground.

25

AVDD

(XT-VDD)

Analog power supply.

26

NC

Not connected.

27

NC

Not connected.

28

X2

Crystal oscillator connected between X1 and X2

Note:

( ): For pin11/13/14/17/18/25, die option