PIC12F635-ISLASHST datasheet(48/234 Pages) MICROCHIP

48 / 234 page

PIC12F635/PIC16F636/639

DS41232D-page 46

FIGURE 3-9:

FSCM TIMING DIAGRAM

TABLE 3-2:

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

OSFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note:

The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

Test

Clock Monitor Output

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets(1)

CONFIG(2)

CPD

MCLRE

PWRTE

WDTE

FOSC2

FOSC1

FOSC0

—

INTCON

GIE

PEIE

T0IE

INTE

RAIE

T0IF

INTF

RAIF

0000 000x

OSCCON

—

IRCF2

IRCF1

IRCF0

OSTS

HTS

LTS

SCS

-110 x000

OSCTUNE

—

TUN4

TUN3

TUN2

TUN1

TUN0

---0 0000

---u uuuu

PIE1

EEIE

LVDIE

CRIE

C2IE(3)

C1IE

OSFIE

—

TMR1IE

000- 00-0

PIR1

EEIF

LVDIF

CRIF

C2IF(3)

C1IF

OSFIF

—

TMR1IF

000- 00-0

Legend:

= unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.

Note

Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

See Configuration Word register (CONFIG) for operation of all register bits.

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