COP8SCE9HMT7 datasheet(32/70 Pages) NSC

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7.0 Power Saving Features (Continued)

7.1 POWER SAVE MODE CONTROL REGISTER

The ITMR control register allows for navigation between the

three different modes of operation. It is also used for the Idle

Timer. The register bit assignments are shown below. This

LSON

HSON

DCEN

CCK

SEL

RSVD

ITSEL2

ITSEL1

ITSEL0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LSON:

This bit is used to turn-on the low-speed oscilla-

tor. When LSON = 0, the low speed oscillator is

off. When LSON = 1, the low speed oscillator is

on. There is a startup time associated with this

oscillator. See the Oscillator Circuits section.

HSON:

This bit is used to turn-on the high speed oscil-

lator. When HSON = 0, the high speed oscillator

is off. When HSON = 1, the high speed oscillator

is on. There is a startup time associated with this

oscillator. See the startup time table in the Os-

cillator Circuits section.

DCEN:

This bit selects the clock source for the Idle

Timer. If this bit = 0, then the high speed clock is

the clock source for the Idle Timer. If this bit = 1,

then the low speed clock is the clock source for

the Idle Timer. The low speed oscillator must be

started and stabilized before setting this bit to a

CCKSEL: This bit selects whether the high speed clock or

low speed clock is gated to the microcontroller

core. When this bit = 0, the Core clock will be the

high speed clock. When this bit = 1, then the

Core clock will be the low speed clock. Before

switching this bit to either state, the appropriate

clock should be turned on and stabilized.

DCEN CCKSEL

High Speed Mode. Core and Idle Timer

Clock = High Speed

Dual Clock Mode. Core clock = High

Speed; Idle Timer = Low Speed

Low Speed Mode. Core and Idle Timer

Clock = Low Speed

Invalid. If this is detected, the Low

Speed Mode will be forced.

RSVD:

This bit is reserved and must be 0.

Bits 2–0: These are bits used to control the Idle Timer. See

6.1 TIMER T0 (IDLE TIMER) for the description

of these bits.

Table 17 lists the valid contents for the four most significant

bits of the ITMR Register. Any other value is illegal and will

result in an unrecoverable loss of a clock to the CPU core. To

prevent this condition, the device will automatically reset if

any illegal value is detected.

TABLE 17. Valid Contents of Dual Clock Control Bits

LSON HSON DCEN CCKSEL

Mode

High Speed

High Speed/Dual

Clock Transition

Dual Clock

Dual Clock/Low

Speed Transition

Low Speed

This internal reset presets the Idle Timer to 00Fx which

results in an internal reset of 240 to 256 t

C. This delay is

independent of oscillator type and the state of BOR enable.

20032722

FIGURE 19. Diagram of Power Save Modes

COP8SCE9HMT7 Datasheet(PDF) 32 Page - National Semiconductor (TI)

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