OP467AYSLASH883C datasheet(13/20 Pages) AD

13 / 20 page

OP467

Rev. | Page 13 of 20

APPLICATIONS INFORMATION

OUTPUT SHORT-CIRCUIT PERFORMANCE

To achieve a wide bandwidth and high slew rate, the OP467

output is not short-circuit protected. Shorting the output to

ground or to the supplies may destroy the device.

For safe operation, the output load current should be limited so

that the junction temperature does not exceed the absolute

maximum junction temperature.

The maximum internal power dissipation can be calculated by

−

max

where:

TJ and TA are junction and ambient temperatures, respectively.

PD is device internal power dissipation.

θJA is the packaged device thermal resistance given in the data sheet.

UNUSED AMPLIFIERS

It is recommended that any unused amplifiers in the quad

package be connected as a unity-gain follower with a 1 kΩ

feedback resistor with noninverting input tied to the ground plain.

PCB LAYOUT CONSIDERATIONS

Satisfactory performance of a high speed op amp largely

depends on a good PCB layout. To achieve the best dynamic

performance, follow the high frequency layout technique.

GROUNDING

A good ground plain is essential to achieve the optimum

performance in high speed applications. It can significantly

reduce the undesirable effects of ground loops and IR drops by

providing a low impedance reference point. Best results are

obtained with a multilayer board design with one layer assigned

to the ground plain. To maintain a continuous and low impedance

ground, avoid running any traces on this layer.

POWER SUPPLY CONSIDERATIONS

In high frequency circuits, device lead length introduces an

inductance in series with the circuit. This inductance, combined

with stray capacitance, forms a high frequency resonance circuit.

Poles generated by these circuits cause gain peaking and additional

phase shift, reducing the phase margin of the op amp and leading

to an unstable operation.

A practical solution to this problem is to reduce the resonance

frequency low enough to take advantage of the power supply

rejection of the amplifier. This is easily done by placing capacitors

across the supply line and the ground plane as close as possible

to the device pin. Because capacitors also have internal parasitic

components, such as stray inductance, selecting the right capacitor

is important. To be effective, they should have low impedance

over the frequency range of interest. Tantalum capacitors are an

excellent choice for their high capacitance/size ratio, but their

effective series resistance (ESR) increases with frequency

making them less effective.

On the other hand, ceramic chip capacitors have excellent ESR

and effective series inductance (ESL) performance at higher

frequencies, and because of their small size, they can be placed

very close to the device pin, further reducing the stray inductance.

Best results are achieved by using a combination of these two

capacitors. A 5 μF to 10 μF tantalum parallel capacitor with a

0.1 μF ceramic chip capacitor is recommended. If additional

isolation from high frequency resonances of the power supply is

needed, a ferrite bead should be placed in series with the supply

lines between the bypass capacitors and the power supply. Note

that addition of the ferrite bead introduces a new pole and zero

to the frequency response of the circuit and could cause unstable

operation if it is not selected properly.

+VS

10µF TANTALUM

0.1µF CERAMIC CHIP

–VS

10µF TANTALUM

0.1µF CERAMIC CHIP

Figure 40. Recommended Power Supply Bypass

SIGNAL CONSIDERATIONS

Input and output traces need special attention to assure a

minimum stray capacitance. Input nodes are very sensitive to

capacitive reactance, particularly when connected to a high

impedance circuit. Stray capacitance can inject undesirable

signals from a noisy line into a high impedance input. Protect

high impedance input traces by providing guard traces around

them, which also improves the channel separation significantly.

Additionally, any stray capacitance in parallel with the input

capacitance of the op amp generates a pole in the frequency

response of the circuit. The additional phase shift caused by this

pole reduces the gain margin of the circuit. If this pole is within

the gain range of the op amp, it causes unstable performance. To

reduce these undesirable effects, use the lowest impedance

where possible. Lowering the impedance at this node places the

poles at a higher frequency, far above the gain range of the

amplifier. Stray capacitance on the PCB can be reduced by making

the traces narrow and as short as possible. Further reduction

can be realized by choosing a smaller pad size, increasing the

spacing between the traces, and using PCB material with a low

dielectric constant insulator (dielectric constant of some common

insulators: air = 1, Teflon® = 2.2, and FR4 = 4.7, with air being

an ideal insulator).

Removing segments of the ground plane directly under the

input and output pads is recommended.

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