TAS2120 datasheet(20/63 Pages) TI

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Table 6-7. Software Mode Control

MODE[1:0]

Configuration

Device in active mode of

operation

Reserved

10 (default)

Device in software shutdown

mode

Device in Clock based Active and

shutdown mode

TAS2120 can be reset to its default configuration by setting the SW_RESET register to '1'. If the device is

powered up, when the SW_RESET bit is set high, all the channels are powered down immediately. All the

registers are restored to the default state when SW_RESET is set high. This bit is self-clearing and goes back to

'0' once the reset is complete.

The device can also signal to the host once the status of the device reaches Active mode of operation using the

INT_LTCH0[1] bit (Section 6.3.2). This bit is a live device status bit and reflects the device status in real-time.

This bit is set high when the device is in Active mode and set low when the device is in shutdown mode.

6.3.1.4 Efficiency and power saving modes

TAS2120 has multiple power-saving modes of operation designed to achieve the highest system level efficiency

under all operating conditions. The device transitions from one mode to the next based on the configured mode

and the signal condition. The transitions from one mode to another are automatic and designed to ensure

high-performance audio levels during the transition of the modes.

EFFICIENCY_MODE[1:0] register allows for configuration of the Music efficiency and Noise gate modes of

operation

6.3.1.4.1 Noise Gate

When the Noise gate feature is enabled, the device automatically detects periods of silence during active

playback mode and reduces the idle channel power consumption significantly to extend the battery life. This

feature is useful for signals playback having long periods of silence, eg voice calls, movie tracks, etc.

The device monitors the input audio signal level against the programmed Noise gate threshold configured by

the NG_TH_LVL[2:0] register. When the audio signal falls below the threshold, an internal Hysteresis timer

is enabled. If the signal level remains below the configured NG_TH_LVL[2:0] for the entire duration of the

NG_HYST_TIMER[1:0], the device enters into the Noise gate mode and reduces the idle channel power

consumption. In the Noise gate mode of operation, the high switching blocks like class-D PWM output are

turned OFF and outputs are pulled low. The output impedance of class-D can be controlled when the Noise gate

mode is active using the CLASSD_HIZ_MODE register. While the Noise gate mode is active, class-D outputs

are not switching and the device does not produce any audio output signal. When the device is in Noise gate

mode, the NG_STATUS bit is set as high and when the device comes out of noise gate mode, the status bit is

set to low.

When the signal level increases above the NG_TH_LVL[1:0], the device automatically wakes up the blocks in

low IQ mode and starts playing out the audio input signals. The wake up from Noise gate maintains the signal

fidelity by buffering the input signal data during the transition time from noise gate mode to active playback

mode. The device does not lose any audio input samples while transitioning from noise gate to active playback.

The transition into noise gate mode and recovery out of noise gate mode is designed to be click and pop-free by

following the proper shutdown and power up sequencing.

TAS2120

SLASFC6 – AUGUST 2024

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