TLV9064IPWR datasheet(5/93 Pages) TI

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+IN

V+

V±

SHDN

OUT

Not to scale

±IN

Figure 4-4. TLV9061S DBV Package, 6-Pin SOT-23

(Top View)

+IN

V+

V±

SHDN

OUT

Not to scale

±IN

Figure 4-5. TLV9061S DRY Package, 6-Pin USON

(Top View)

Table 4-2. Pin Functions: TLV9061S

TYPE(1)

DESCRIPTION

NAME

SOT-23

USON

IN–

Inverting input

IN+

Noninverting input

OUT

Output

SHDN

Shutdown: low = amp disabled, high = amp enabled. See Shutdown Function

section for more information.

V–

I or — Negative (low) supply or ground (for single-supply operation)

V+

Positive (high) supply

(1)

I = input, O = output

OUT1

V+

IN1±

OUT2

IN1+

IN2±

V±

IN2+

Not to scale

Figure 4-6. TLV9062 D, DGK, PW, or DDF Package,

8-Pin SOIC, VSSOP, TSSOP, or SOT-23 (Top View)

OUT1

V+

IN1±

OUT2

IN1+

IN2±

V±

IN2+

Not to scale

Thermal

Pad

Connect thermal pad to V–

Figure 4-7. TLV9062 DSG Package, 8-Pin WSON

With Exposed Thermal Pad (Top View)

Table 4-3. Pin Functions: TLV9062

TYPE(1)

DESCRIPTION

NAME

NO.

IN1–

Inverting input, channel 1

IN1+

Noninverting input, channel 1

IN2–

Inverting input, channel 2

IN2+

Noninverting input, channel 2

OUT1

Output, channel 1

OUT2

Output, channel 2

V–

—

Negative (lowest) supply or ground (for single-supply operation)

V+

—

Positive (highest) supply

(1)

I = input, O = output

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TLV9061, TLV9062, TLV9064

SBOS839L – MARCH 2017 – REVISED SEPTEMBER 2024

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