PACE1757ME datasheet(7/34 Pages) PYRAMID

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PACE 1757 M/ME

Page 7 of 34

Document # MICRO-10 REV B

TIMING GENERATOR STATE DIAGRAMS

Two separate and almost independent state diagrams

may be used to describe the PACE1757ME machine

cycle.

The Execution Unit performs according to a cycle of

three states represented by Diagram A (the A machine)

and the External Bus Unit follows a minimum cycle of

four states, indicated in Diagram B (the B machine).

Referring to Diagram A, the paths are defined as

follows for the Execution Unit:

(0) External Reset true

(1) External Reset false

(2) ALU wait or Bus wait.

(3) ALU Branch false

(4) ALU Branch true

Diagram B defines the paths for the External Bus as

follows:

(0) External Rest false

(1) No Internal Bus Req.

(2) Internal Bus Req.

(3) Bus Busy or No Bus Grant

(4) Bus Grant and Not Busy or

Bus Locked by CPU

(5) RDYA false

(6) RDYA true

(7) RDYD false

(8) RDYD true, and no Internal Bus Request

(9) RDYD true, Internal Bus Request pending

(10) Bus Locked by CPU and No Internal Request

(11) Bus Locked by CPU Internal Req.

NOTE:

Bus AV = Bus grant and Bus not busy and Bus not locked.

Diagram A

Diagram B

PACE1757ME Datasheet(PDF) 7 Page - Pyramid Semiconductor Corporation