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CS5345 Datasheet(PDF) 21 Page - Cirrus Logic |
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CS5345 Datasheet(HTML) 21 Page - Cirrus Logic |
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21 / 41 page  DS658F2 21 CS5345 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL =30pF. 21. Data must be held for sufficient time to bridge the transition time of CCLK. 22. For fsck <1 MHz. Parameter Symbol Min Max Units CCLK Clock Frequency fsck -6.0 MHz RESET Rising Edge to CS Falling tsrs 500 - ns CS High Time Between Transmissions tcsh 1.0 - μs CS Falling to CCLK Edge tcss 20 - ns CCLK Low Time tscl 66 - ns CCLK High Time tsch 66 - ns CDIN to CCLK Rising Setup Time tdsu 40 - ns CCLK Rising to DATA Hold Time (Note 21) tdh 15 - ns CCLK Falling to CDOUT Stable tpd -50 ns Rise Time of CDOUT tr1 -25 ns Fall Time of CDOUT tf1 -25 ns Rise Time of CCLK and CDIN (Note 22) tr2 - 100 ns Fall Time of CCLK and CDIN (Note 22) tf2 - 100 ns t r2 t f2 t dsu t dh t sch t scl CS CCLK CDIN t css t pd CDOUT t csh RST t srs Figure 6. Control Port Timing - SPI Format |
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