Integrated

Circuit

Systems, Inc.

ICS97ULP877A

7116—03/27/07

Block Diagram

1.8V Low-Power Wide-Range Frequency Clock Driver

Pin Configuration

40-Pin MLF

Recommended Application:

•

DDR2 Memory Modules / Zero Delay Board Fan Out

•

Provides complete DDR DIMM logic solution with

ICSSSTU32864/SSTUF32864/SSTUF32866/

SSTUA32864/SSTUA32866/SSTUA32S868/

SSTUA32S865/SSTUA32S869

Product Description/Features:

•

Low skew, low jitter PLL clock driver

•

1 to 10 differential clock distribution (SSTL_18)

•

Feedback pins for input to output synchronization

•

Spread Spectrum tolerant inputs

•

Auto PD when input signal is at a certain logic state

Switching Characteristics:

•

Period jitter: 40ps (DDR2-400/533)

30ps (DDR2-667)

•

Half-period jitter: 60ps (DDR2-400/533)

50ps (DDR2-667)

•

OUTPUT - OUTPUT skew: 40ps (DDR2-400/533)

30ps (DDR2-667)

•

CYCLE - CYCLE jitter 40ps

52-Ball BGA

Top View

12345

6

A

CLKT1

CLKT0

CLKC0

CLKC5

CLKT5

CLKT6

B

CLKC1

GND

GND

GND

GND

CLKC6

C

CLKC2

GND

NB

NB

GND

CLKC7

D

CLKT2

VDDQ

VDDQ

VDDQ

OS

CLKT7

E

CLK_INT

VDDQ

NB

NB

VDDQ

FB_INT

F

CLK_INC

VDDQ

NB

NB

OE

FB_INC

G

AGND

VDDQ

VDDQ

VDDQ

VDDQ

FB_OUTC

H

AVDD

GND

NB

NB

GND

FB_OUTT

J

CLKT3

GND

GND

GND

GND

CLKT8

K

CLKC3

CLKC4

CLKT4

CLKT9

CLKC9

CLKC8

A

B

C

D

E

F

G

H

J

K

6

5

4

3

2

1

CLKT2

CLK_INT

GND

CLKC2

CLK_INC

AGND

2

3

4

5

6

7

8

9

10

1

22

23

24

30

29

28

27

26

25

21

FB_INT

OS

CLKT7

FB_INC

OE

FB_OUTT

FB_OUTC

CLKC7

CLKT0

CLKC0

CLKT1

CLKC1

CLKT2

CLKC2

CLKT3

CLKC3

CLKT4

CLKC4

CLKT5

CLKC5

CLKT6

CLKC6

CLKT7

CLKC7

CLKT8

CLKC8

CLKT9

CLKC9

FB_OUTT

FB_OUTC

Powerdown

Control and

Test Logic

LD

or OE

(1)

LD , OS, or OE

(1)

OS

OE

LD

(1)

PLL Bypass

PLL

FB_INT

FB_INC

GND

CLK_INT

CLK_INC

NOTE:

1. The Logic Detect (LD) powers down the device when a logic LOW is

applied to both CLK_INT and CLK+INC.