ADS1625IPAPRG4 datasheet(8/37 Pages) TI

Part #	ADS1625IPAPRG4

Description	18-Bit, 1.25MSPS Analog-to-Digital Converter

PDF	37 Pages

Scroll/Zoom	100%

Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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8 / 37 page

ADS1625

ADS1626

SBAS280E − JUNE 2003 − REVISED MAY 2007

www.ti.com

PARAMETER MEASUREMENT INFORMATION

DRDY

CLK

DOUT[17:0]

Data N + 1

NOTE: CS and RD tied low.

Data N

Data N + 2

Figure 1. Data Retrieval Timing (ADS1625, ADS1626 with FIFO Disabled)

RD, CS

DOUT[17:0]

Figure 2. DOUT Inactive/Active Timing (ADS1625, ADS1626 with FIFO Disabled)

TIMING REQUIREMENTS FOR FIGURE 1 AND FIGURE 2

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

CLK period (1/fCLK)

1000

1/t1

fCLK

MHz

CLK pulse width, high or low

Rising edge of CLK to DRDY low

DRDY pulse width high or low

16 t1

Falling edge of DRDY to data invalid

Falling edge of DRDY to data valid

Rising edge of RD and/or CS inactive (high) to DOUT high impedance

Falling edge of RD and/or CS active (low) to DOUT active.

NOTE: DOUT[17:0] and DRDY load = 10pF.

ADS1625IPAPRG4 Datasheet(PDF) 8 Page - Texas Instruments