P4C1023L-70CWC datasheet(6/11 Pages) PYRAMID

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P4C1023/P4C1023L

Page 6 of 11

Document # SRAM126 REV OR

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TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE

CE CONTROLLED)(6)

* including scope and test fixture.

Note:

Because of the high speed of the P4C1023L, care must be taken when

testing this device; an inadequate setup can cause a normal function-

ing part to be rejected as faulty. Long high-inductance leads that cause

supply bounce must be avoided by bringing the V

CC and ground planes

directly up to the contactor fingers. A 0.01 µF high frequency capacitor

is also required between V

CC and ground.

To avoid signal reflections, proper termination must be used; for

example, a 50

Ω test environment should be terminated into a 50Ω

load with 1.77V (Thevenin Voltage) at the comparator input, and a

589

Ω resistor must be used in series with D

OUT to match 639Ω

(Thevenin Resistance).

AC TEST CONDITIONS

TRUTH TABLE

Input Pulse Levels

Input Rise and Fall Times

Input Timing Reference Level

Output Timing Reference Level

Output Load

GND to 3.0V

3ns

1.5V

See Figures 1 and 2

Mode

Standby

OUT Disabled

Standby

Power

I/O

High Z

OUT

Active

High Z

P4C1023L-70CWC Datasheet(PDF) 6 Page - Pyramid Semiconductor Corporation

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