LM4040D82ILPR datasheet(28/58 Pages) TI

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8.2.2.3 Output Capacitor

The LM4040 does not require an output capacitor across cathode and anode for stability. However, if an output

bypass capacitor is desired, the LM4040 is designed to be stable with all capacitive loads.

8.2.2.4 SOT-23 Connections

There is a parasitic Schottky diode connected between pins 2 and 3 of the SOT-23 packaged device. Thus, pin 3

of the SOT-23 package must be left floating or connected to pin 2.

8.2.2.5 Start-Up Characteristics

In any data conversion system, start-up characteristics are important, as to determine when it is safe begin

conversion based upon a steady and settled reference value. As shown in Figure 8-4 it is best to allow for >20µs

from supply start-up to begin conversion.

1 Hz Rate

LM4040

VIN

Figure 8-3. Test Circuit

8.2.3 Application Curve

−1

−10

VZ = 2.5 V

TJ = 25°C

RS = 30 kW

Response Time (ms)

VIN

−2

−4

−6

−8

−10

−12

Figure 8-4. Startup Response

8.3 Power Supply Recommendations

To not exceed the maximum cathode current, be sure that the supply voltage is current limited.

For applications shunting high currents (15mA max), pay attention to the cathode and anode trace lengths,

adjusting the width of the traces to have the proper current density.

8.4 Layout

8.4.1 Layout Guidelines

Figure 8-5 shows an example of a PCB layout of LM4040XXXDBZ. Some key Vref noise considerations are:

• Connect a low-ESR, 0.1-μF (CL) ceramic bypass capacitor on the cathode pin node.

• Decouple other active devices in the system per the device specifications.

• Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise

pickup.

LM4040A, LM4040B, LM4040C, LM4040D

SLOS456O – JANUARY 2005 – REVISED JUNE 2024

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